參數(shù)資料
型號(hào)： LMX2331LSLBX
英文描述： Serial-Input Frequency Synthesizer
中文描述： 串行輸入頻率合成器
文件頁(yè)數(shù)： 10/19頁(yè)
文件大?。?/td> 362K
代理商： LMX2331LSLBX
1.0 Functional Description
(Continued)
1.3.1 POWERDOWN OPERATION
Bits F[2] and F[18] provide programmable powerdown modes when the CE pin is HIGH. When CE is LOW, the part is always im-
mediately disabled regardless of powerdown bit status. Refer to Table 3
Synchronous and asynchronous powerdown modes are both available by MICROWIRE selection. Synchronous powerdown oc-
curs if the F[18] bit (Powerdown Mode) is HIGH when F[2] bit (Powerdown) becomes HIGH. Asynchronous powerdown occurs
if the F[18] bit is LOW when its F[2] bit becomes HIGH.
In the synchronous powerdown mode (F[18] = HIGH), the powerdown function is gated by the charge pump to prevent unwanted
frequency jumps. Once the powerdown program bit F[2] is loaded, the part will go into powerdown mode after the first successive
charge pump event.
In the asynchronous powerdown mode (F[18] = LOW), the device powers down immediately after latching LOW data into bit F[2].
The device returns to an actively powered up condition in either synchronous or asynchronous mode immediately upon LE latch-
ing LOW data into bit F[2].
Activation of a powerdown condition in either synchronous or asynchronous mode including CE pin activated powerdown has the
following effects:
Removes all active DC current paths.
Forces the R, N, and timeout counters to their load state
conditions.
Will TRI-STATE the charge pump.
Resets the digital lock detect circuitry.
Debiases the f
IN
input to a high impedance state.
Disables the oscillator input buffer circuitry.
The MICROWIRE control register remains active and ca-
pable of loading the data.
TABLE 3. Power Down Truth Table
CE(Pin 10)
F[2]
X
0
1
1
F[18]
X
X
0
1
Mode
LOW
HIGH
HIGH
HIGH
Asynchronous Power Down
Normal Operation
Asynchronous Power Down
Synchronous Power Down
TABLE 4. The Fo/LD (pin 14) Output Truth Table
F[3]
0
0
0
0
1
1
F[4]
0
0
1
1
0
0
F[5]
0
1
0
1
0
1
Fo/LD Output State
TRI-STATE
R Divider Output (fr)
N Divider Output (fp)
Serial Data Output
Digital Lock Detect (See 1.3.2 LOCK DETECT OUTPUT Section)
n Channel Open Drain Lock Detect (See 1.3.2 LOCK DETECT OUTPUT
Section)
Active HIGH
Active LOW
1
1
1
1
0
1
L
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