參數(shù)資料
型號(hào)： LMX2330ATMX
英文描述： Serial-Input Frequency Synthesizer
中文描述： 串行輸入頻率合成器
文件頁數(shù)： 13/19頁
文件大?。?/td> 362K
代理商： LMX2330ATMX
1.0 Functional Description
(Continued)
TABLE 6. FastLock Timeout Counter Value Programming
Timeout
(
#
PD Cycles)
(Note 8)
F11
(4)
F12
(8)
F13
(16)
F14
(32)
3
7
11
15
19
23
27
31
35
59
63
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
Note 8:
The timeout counter decrements after each phase detector comparison cycle.
1.4 SERIAL DATA INPUT TIMING
1.5 PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
DS100127-9
Notes:
Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
TEST CONDITIONS:
The Serial Data Input Timing is tested using a symmetrical waveform around V
CC/2
. The test waveform has an edge rate of 0.6V/ns with
amplitudes of 1.84V
@
V
CC
= 2.3V and 4.4V
@
V
CC
= 5.5V.
DS100127-10
Notes:
Phase difference detection range: 2
π
to +2
π
The Phase Detector Polarity F[6] = HIGH
The minimum width pump up and pump down current pulses occur at the ICP
o
pin when the loop is locked.
L
www.national.com
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