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參數(shù)資料
| 型號： | LMX2324ASLBX |
| 英文描述： | FREQUENCY SYNTHESIZER|BICMOS|LLCC|16PIN|PLASTIC |
| 中文描述： | 頻率合成器| BICMOS工藝| LLCC | 16PIN |塑料 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 362K |
| 代理商： | LMX2324ASLBX |
1.0 Functional Description
(Continued)
1.3 FUNCTION AND INITIALIZATION LATCHES
Both the function and initialization latches write to the same registers. (See Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING V
CC
section for initialization latch description.)
TABLE 1. Programmable Modes
C1
0
C2
1
F1
F2
F3–5
FoLD
CONTROL
F6
PD
F7
CP
F8
COUNTER
RESET
POWER DOWN
FASTLOCK
ENABLE
POLARITY
TRI-STATE
F9
F10
F11–14
TIMEOUT
COUNTER
VALUE
F15–F17
TEST
MODES
F18
FAST-
LOCK
CONTROL
TIMEOUT
COUNTER
ENABLE
POWER
DOWN
MODE
TABLE 2. Mode Select Truth Table
REGISTER
LEVEL
COUNTER
RESET
POWER
DOWN
PHASE
DETECTOR
POLARITY
NEGATIVE
CP
TRI-STATE
0
RESET
DISABLED
RESET
ENABELED
POWERED
UP
POWERED
DOWN
NORMAL
OPERATION
TRI-STATE
1
POSITIVE
FUNCTION DESCRIPTION
F1.
The
Counter Reset
enable mode bit F1, when activated, allows the reset of both N and R counters. Upon powering up, the
F1 bit needs to be disabled, then the N counter resumes counting in “close” alignment with the R counter. (The maximum error
is one prescalar cycle).
F2.
Refer to Section 1.3.1 POWERDOWN OPERATION section.
F3–5.
Controls output of
FoLD
pin. See FoLD truth table. See Table 4
F6. Phase Detector Polarity.
Depending upon VCO characteristics, F6 bit should be set accordingly. When VCO characteristics
are positive F6 should be set HIGH; When VCO characteristics are negative F6 should be set LOW
F7. Charge Pump TRI-STATE
is set using bit F7. For normal operation this bit is set to zero.
F8.
When the
FastLock Enable
bit is set the part is forced into one of the four FastLock modes. See description in Table 5 Fast-
Lock Decoding.
F9.
The
FastLock Control
bit determines the mode of operation when in FastLock (F8 = 1). When not in FastLock mode, FL
o
can be used as a general purpose output controlled by this bit. For F9 = 1, FL
o
is HIGH and for F9 = 0, FL
o
is LOW. See Table
5 for truth table.
F10. Timeout Counter Enable
bit is set to 1 to enable the timeout counter. See Table 5 for truth table.
F11–14. FastLock Timeout Counter
is set using bits F11-14. Table 6 for counter values.
F15–17.
Function bits F15–F17 are for
Test Modes
, and should be set to 0 for normal use.
F18.
Refer to Section 1.3.1 POWERDOWN OPERATION section.
DS100127-7
L
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