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參數(shù)資料
| 型號： | LMX2315TMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20 |
| 封裝： | 0.173 INCH, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 409K |
| 代理商： | LMX2315TMX |
Connection Diagrams
LMX2315/LMX2320/LMX2325
TL/W/12339–2
20-Lead (0.173
×
Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2315TM, LMX2315TMX, LMX2325TM, LMX2325TMX, LMX2320TM or LMX2320TMX
See NS Package Number MTC20
Pin Descriptions
Pin No.
Pin Name
I/O
Description
1
OSC
IN
I
Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for
operation as an oscillator. The input has a V
CC
/2 input threshold and can be driven from an external
CMOS or TTL logic gate. May also be used as a buffer for an externally provided reference oscillator.
3
OSC
OUT
O
Oscillator output.
4
V
P
Power supply for charge pump. Must be
t
V
CC
.
5
V
CC
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors should be placed
as close as possible to this pin and be connected directly to the ground plane.
6
D
o
O
Internal charge pump output. For connection to a loop filter for driving the input of an external VCO.
7
GND
Ground.
8
LD
O
Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is
locked, the pin’s output is HIGH with narrow low pulses.
10
f
IN
I
Prescaler input. Small signal input from the VCO.
11
CLOCK
I
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various counters
and registers.
13
DATA
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input.
14
LE
I
Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the shift
registers is loaded into the appropriate latch (control bit dependent). Clock must be low when LE
toggles high or low. See Serial Data Input Timing Diagram.
15
FC
I
Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase
comparator and charge pump combination is reversed.
16
BISW
O
Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge pump
output through BISW (as well as through D
o
).
17
f
OUT
O
Monitor pin of phase comparator input. CMOS output.
18
w
p
O
Output for external charge pump.
w
p
is an open drain N-channel transistor and requires a pull-up
resistor.
19
PWDN
I
Power Down (with internal pull-up resistor).
PWDN
e
HIGH for normal operation.
PWDN
e
LOW for power saving.
Power down function is gated by the return of the charge pump to a TRI-STATE
é
condition.
20
w
r
O
Output for external charge pump.
w
r
is a CMOS logic output.
2,9,12
NC
No connect.
http://www.national.com
2
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