Supply Voltage (V
參數(shù)資料
型號： LMH6643MMX/NOPB
廠商： National Semiconductor
文件頁數(shù)： 23/33頁
文件大?。?/td> 0K
描述： IC OP AMP R-R LP 3V 75MA 8-MSOP
標準包裝： 3,500
系列： PowerWise®
放大器類型： 電壓反饋
電路數(shù)： 2
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 135 V/µs
-3db帶寬： 130MHz
電流 - 輸入偏壓： 1.6µA
電壓 - 輸入偏移： 1000µV
電流 - 電源： 2.7mA
電流 - 輸出 / 通道： 75mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 12.8 V，±1.35 V ~ 6.4 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應商設備封裝： 8-MSOP
包裝： 帶卷 (TR)
其它名稱： LMH6643MMX
LMH6643MMX-ND
LMH6643MMX/NOPBTR
SNOS966P – MAY 2001 – REVISED MARCH 2013
Operating Ratings
(1)
Supply Voltage (V+ – V)
2.7V to 12.8V
Junction Temperature Range (2)
40°C to +85°C
Package Thermal Resistance (2) (
θJA)
5-Pin SOT-23
265°C/W
8-Pin SOIC
190°C/W
8-Pin VSSOP
235°C/W
14-Pin SOIC
145°C/W
14- Pin TSSOP
155°C/W
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2)
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
3V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at TJ = 25°C, V
+ = 3V, V = 0V, V
CM = VO = V
+/2, V
ID (input differential
voltage) as noted (where applicable) and RL = 2k to V
+/2. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(1)
(2)
(1)
BW
3dB BW
AV = +1, VOUT = 200mVPP
80
115
MHz
AV = +2, 1, VOUT = 200mVPP
46
BW0.1dB
0.1dB Gain Flatness
AV = +2, RL = 150 to V+/2,
19
MHz
RL = 402, VOUT = 200mVPP
PBW
Full Power Bandwidth
AV = +1, 1dB, VOUT = 1VPP
40
MHz
en
Input-Referred Voltage Noise
f = 100kHz
17
nV/
√Hz
f = 1kHz
48
in
Input-Referred Current Noise
f = 100kHz
0.90
pA/
√Hz
f = 1kHz
3.3
THD
Total Harmonic Distortion
f = 5MHz, VO = 2VPP, AV = 1,
48
dBc
RL = 100 to V
+/2
DG
Differential Gain
VCM = 1V, NTSC, AV = +2
0.17
RL =150 to V
+/2
%
RL =1k to V
+/2
0.03
DP
Differential Phase
VCM = 1V, NTSC, AV = +2
0.05
RL =150 to V
+/2
deg
RL =1k to V
+/2
0.03
CT Rej.
Cross-Talk Rejection
f = 5MHz, Receiver:
47
dB
Rf = Rg = 510, AV = +2
TS
Settling Time
VO = 2VPP, ±0.1%, 8pF Load,
68
ns
VS = 5V
SR
Slew Rate (3)
AV = 1, VI = 2VPP
90
120
V/s
VOS
Input Offset Voltage
For LMH6642 and LMH6644
±1
±5
±7
mV
For LMH6643
±1
±3.4
±7
TC VOS
Input Offset Average Drift
See (4)
±5
V/°C
IB
Input Bias Current
See (5)
1.50
2.60
A
3.25
IOS
Input Offset Current
20
800
nA
1000
RIN
Common Mode Input Resistance
3
M
(1)
All limits are guaranteed by testing or statistical analysis.
(2)
Typical values represent the most likely parametric norm.
(3)
Slew rate is the average of the rising and falling slew rates.
(4)
Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
(5)
Positive current corresponds to current flowing into the device.
Copyright 2001–2013, Texas Instruments Incorporated
3
Product Folder Links: LMH6642 LMH6643 LMH6644
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