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參數(shù)資料
| 型號： | LMF60CMJ-50 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬濾波器 |
| 英文描述： | LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
| 中文描述： | SWITCHED CAPACITOR FILTER, BUTTERWORTH, LOWPASS, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 391K |
| 代理商： | LMF60CMJ-50 |
Crosstalk Test Circuits
From Filter to Op-Amps
TL/H/9294–6
From Either Op-Amp to Filter Output
TL/H/9294–7
Pin Description
(Pin Numbers)
Pin
Description
FILTER OUT (3)
The output of the lowpass filter will typi-
cally swing to within 1V of each supply
rail.
FILTER IN (8)
The input to the lowpass filter. To mini-
mize gain errors the source impedance
that drives this input should be less than
2k (See Section 1.4). For single supply
operation the input signal must be bi-
ased to mid-supply or AC coupled.
V
OS
ADJ (7)
This pin is used to adjust the DC offset
of the filter output; if not used it must be
tied to the AGND potential. (See Section
1.3)
AGND (5)
The analog ground pin. This pin sets the
DC bias level for the filter section and
the noninverting input of Op-Amp
Y
1
and must be tied to the system ground
for split supply operation or to mid-sup-
ply for single supply operation (See Sec-
tion 1.2). When tied to mid-supply this
pin should be well bypassed.
V
O1
(4),
INV1 (13)
V
O1
is the output and INV1 is the invert-
ing input of Op-Amp
Y
1. The non-invert-
ing input of this Op-Amp is internally
connected to the AGND pin.
V
O2
(2),
INV2 (14),
NINV2 (1)
V
a
(6), V
b
(10)
V
O2
is the output, INV2 is the inverting
input, and NINV2 is the non-inverting in-
put of Op-Amp
Y
2.
The positive and negative supply pins.
The total power supply range is 4V to
14V. Decoupling these pins with 0.1
m
F
capacitors is highly recommended.
Pin
Description
CLK IN (9)
A CMOS Schmitt-trigger input to be
used with an external CMOS logic level
clock.
Also
used
Schmitt-trigger oscillator (See Section
1.1).
for
self-clocking
CLK R (11)
A TTL logic level clock input when in
split supply operation (
g
2V to
g
7V) and
L. Sh tied to system ground. This pin be-
comes a low impedance output when
L.Sh is tied to V
b
. Also used in conjunc-
tion with the CLK IN pin for self clocking
Schmitt-trigger oscillator (See Section
1.1).
L.Sh (12)
Level shift pin, selects the logic thresh-
old levels for the desired clock. When
tied to V
b
it enables an internal TRI-
STATE
é
buffer
stage
Schmitt trigger and the internal clock
level shift stage thus enabling the CLK
IN Schmitt-trigger input and making the
CLK R pin a low impedance output.
between
the
When the voltage level at this input ex-
ceeds
[
25% (V
a
b
V
b
)
a
V
b
]
the in-
ternal TRI-STATE
é
buffer is disabled al-
lowing the CLK R pin to become the
clock input for the internal clock level
shift stage. The CLK R threshold level is
now 2V above the voltage applied to the
L.Sh pin. Driving the CLK R pin with TTL
logic
levels
can
through the use of split supplies and by
tying the L.Sh pin to system ground.
be
accomplished
http://www.national.com
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMF60CIN-100 | LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
| LMF60CIN-50 | LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
| LMF60CIWM-50 | LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
| LMF60CIWM-100 | LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
| LMF60 | LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMF60CMJ-50/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Filter |
| LMF6A602W2851 | 制造商:Vishay Dale 功能描述:KIT LM F 6 A 602 W02851 E3 - Rail/Tube |
| LMF6D202W2851 | 制造商:Vishay Dale 功能描述:KIT LM F 6 D 202 W02851 E3 - Rail/Tube |
| LMF6D502W2851 | 制造商:Vishay Dale 功能描述:KIT LM F 6 D 502 W02851 E3 - Rail/Tube |
| LMF6E153W2851 | 制造商:Vishay Dale 功能描述:KIT LM F 6 E 153 W02851 E3 - Rail/Tube |
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