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參數(shù)資料
| 型號： | LMF60CIWM-100 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬濾波器 |
| 英文描述： | LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
| 中文描述： | SWITCHED CAPACITOR FILTER, BUTTERWORTH, LOWPASS, PDSO14 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-14 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 391K |
| 代理商： | LMF60CIWM-100 |
1.0 LMF60 Application Hints
The LMF60 is comprised of a non-inverting unity gain low-
pass sixth-order Butterworth switched capacitor filter sec-
tion and two undedicated CMOS Op-Amps. The switched-
capacitor topology makes the cutoff frequency (where the
gain drops 3.01 dB below the DC gain) a direct ratio (100:1
or 50:1) of the clock frequency supplied to the lowpass filter.
Internal integrator time constants set the filter’s cutoff fre-
quency. The resistive element of these integrators is actual-
ly a capacitor which is ‘‘switched’’ at the clock frequency
(for a detailed discussion see Input Impedance section).
Varying the clock frequency changes the value of this resis-
tive element and thus the time constant of the integrators.
The clock to cutoff frequency ratio (f
CLK
/f
C
) is set by the
ratio of the input and feedback capacitors in the integrators.
The higher the clock to cutoff frequency ratio (or the sam-
pling rate) the closer the approximation is to the theoretical
Butterworth response. The LMF60 is available in f
CLK
/f
C
ratios of 50:1 (LMF60-50) or 100:1 (LMF60-100).
1.1 CLOCK INPUTS
The LMF60 has a Schmitt-trigger inverting buffer which can
be used to construct a simple R/C oscillator. The oscillator
frequency is dependent on the buffer’s threshold levels as
well as on the resistor/capacitor tolerance (See Figure 1 ).
Schmitt-trigger threshold voltage levels can vary significant-
ly causing the R/C oscillator’s frequency to vary greatly
from part to part.
Where accuracy in f
C
is required an external clock can be
used to drive the CLK R input of the LMF60. This input is
TTL logic level compatible and also presents a very light
load to the external clock source (
E
2
m
A) with split sup-
plies and L.Sh tied to system ground. The logic level is pro-
grammed by the voltage applied to level shift (L.Sh) pin (See
the Pin Description for L.Sh pin).
1.2 POWER SUPPLY BIASING
The LMF60 can be biased from a single supply or dual split
supplies. The split supply mode shown inFigures 2 and3 is
the most flexible and easiest to implement. As discussed
earlier split supplies,
g
2V to
g
7V, will enable the use of
TTL or CMOS clock logic levels. Figure 4 shows two
schemes for single supply biasing. In this mode only CMOS
clock logic levels can be used.
RC In
D#
TL/H/9294–8
f
CLK
e
1
V
CC
b
V
T
b
V
CC
b
V
T
a
J
V
T
a
V
T
b
(
Typically for V
CC
e
V
a
b
V
b
e
10V:
1
f
CLK
e
1.37 RC
FIGURE 1. Schmitt Trigger R/C Oscillator
http://www.national.com
10
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LMF60CIWM-50 | 制造商:Texas Instruments 功能描述: |
| LMF60CMJ-100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
| LMF60CMJ-100/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Filter |
| LMF60CMJ-50 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter |
| LMF60CMJ-50/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Filter |
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