參數(shù)資料
型號: LMC6462BIM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運動控制電子
英文描述: CERAMIC CHIP CAPACITORS 3300PF 50V X7R 10%
中文描述: DUAL OP-AMP, 3000 uV OFFSET-MAX, 0.05 MHz BAND WIDTH, PDSO8
封裝: SOIC-8
文件頁數(shù): 11/18頁
文件大小: 648K
代理商: LMC6462BIM
Application Information
(Continued)
The effect of input capacitance can be compensated for by
adding a feedback capacitor. The feedback capacitor (as in
Figure 8 ), C
F
, is first estimated by:
or
R
1
C
IN
R
2
C
F
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or
smaller than that of a breadboard, so the actual optimum
value for C
may be different. The values of C
should be
checked on the actual circuit. (Refer to the LMC660 quad
CMOS amplifier data sheet for a more detailed discussion.)
5.0 Offset Voltage Adjustment
Offset voltage adjustment circuits are illustrated in Figure 9
and Figure 10 Large value resistances and potentiometers
are used to reduce power consumption while providing typi-
cally
±
2.5 mV of adjustment range, referred to the input, for
both configurations with V
S
=
±
5V.
6.0 Spice Macromodel
A Spice macromodel is available for the LMC6462/4. This
model includes a simulation of:
Input common-mode voltage range
Frequency and transient response
GBW dependence on loading conditions
Quiescent and dynamic supply current
Output swing dependence on loading conditions
and many more characteristics as listed on the macromodel
disk.
Contact the National Semiconductor Customer Response
Center to obtain an operational amplifier Spice model library
disk.
7.0 Printed-Circuit-Board Layout
for High-Impedance Work
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low input current of the LMC6462/4, typically 150
fA, it is essential to have an excellent layout. Fortunately, the
techniques of obtaining low leakages are quite simple. First,
the user must not ignore the surface leakage of the PC
board, even though it may sometimes appear acceptably
low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6462’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs, as in Fig-
ure 11 To have a significant effect, guard rings should be
placed in both the top and bottom of the PC board. This PC
foil must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
12
, which is nor-
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This
would cause a 30 times degradation from the LMC6462/4’s
actual performance. However, if a guard ring is held within 5
mV of the inputs, then even a resistance of 10
11
would
cause only 0.05 pA of leakage current. See Figure 12 for
typical connections of guard rings for standard op-amp
configurations.
DS012051-12
FIGURE 8. Canceling the Effect of Input Capacitance
DS012051-13
FIGURE 9. Inverting Configuration
Offset Voltage Adjustment
DS012051-14
FIGURE 10. Non-Inverting Configuration
Offset Voltage Adjustment
www.national.com
11
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