參數(shù)資料
型號: LMC6024IN
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運算放大器
英文描述: Low Power CMOS Quad Operational Amplifier
中文描述: QUAD OP-AMP, 9000 uV OFFSET-MAX, 0.35 MHz BAND WIDTH, PDIP14
封裝: 0.300 INCH, PLASTIC, DIP-14
文件頁數(shù): 7/14頁
文件大?。?/td> 315K
代理商: LMC6024IN
Typical Performance Characteristics
V
S
=
±
7.5V, T
A
= 25C unless otherwise specified (Continued)
Application Hints
AMPLIFIER TOPOLOGY
The topology chosen for the LMC6024 is unconventional
(compared to general-purpose op amps) in that the tradi-
tional unity-gain buffer output stage is not used; instead, the
output is taken directly from the output of the integrator, to al-
low rail-to-rail output swing. Since the buffer traditionally de-
livers the power to the load, while maintaining high op amp
gain and stability, and must withstand shorts to either rail,
these tasks now fall to the integrator.
As a result of these demands, the integrator is a compound
affair with an embedded gain stage that is doubly fed forward
(via C
and C
) by a dedicated unity-gain compensation
driver. In addition, the output portion of the integrator is a
push-pull configuration for delivering heavy loads. While
sinking current the whole amplifier path consists of three
gain stages with one stage fed forward, whereas while
sourcing the path contains four gain stages with two fed
forward.
The large signal voltage gain while sourcing is comparable
to traditional bipolar op amps, for load resistance of at least
5 k
. The gain while sinking is higher than most CMOS op
amps, due to the additional gain stage; however, when driv-
Non-Inverting Small
Signal Pulse Response
(A
V
= +1)
DS011235-45
Inverting Large-Signal
Pulse Response
DS011235-46
Inverting Small-Signal
Pulse Response
DS011235-47
Stability vs Capacitive Load
DS011235-4
Note 13:
Avoid resistive loads of less than 500
, as they may cause instability.
Stability vs Capacitive Load
DS011235-5
DS011235-6
FIGURE 1. LMC6024 Circuit Topology (Each Amplifier)
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相關代理商/技術參數(shù)
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