參數(shù)資料
型號(hào)： LMC568CN
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Low Power Phase-Locked Loop
中文描述： PHASE LOCKED LOOP, PDIP8
封裝： PLASTIC, DIP-8
文件頁數(shù)： 1/6頁
文件大?。?/td> 161K
代理商： LMC568CN
LMC568
Low Power Phase-Locked Loop
General Description
The LMC568 is an amplitude-linear phase-locked loop con-
sisting of a linear VCO, fully balanced phase detectors, and
a carrier detect output. LMCMOS
technology is employed
for high performance with low power consumption.
The VCO has a linearized control range of
±
30% to allow de-
modulation of FM and FSK signals. Carrier detect is indi-
cated when the PLL is locked to an input signal greater than
26 mVrms. LMC568 applications include FM SCA and TV
second audio program decoders, FSK data demodulators,
and voice pagers.
Features
n
Demodulates
±
15% deviation FM/FSK signals
n
Carrier Detect Output with hysteresis
n
Operation to 500 kHz input frequency
n
Low THD— 0.5% typ. for
±
10% deviation
n
2V to 9V supply voltage range
n
Low supply current drain
Typical Application
(100 kHz input frequency, refer to notes pg. 3)
LMCMOS
is a trademark of National Semiconductor Corporation.
DS009135-1
Order Number LMC568CM or LMC568CN
See NS Package Number M08A or N08E
May 1999
L
1999 National Semiconductor Corporation
DS009135
www.national.com
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