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PGA Gain Plots
Applications Information
ANALOG-TO-DIGITAL CONVERTER REFERENCE
BYPASSING
Figure 17 shows a simple reference bypassing scheme with
minimal components. The V
REFT
and V
REFB
pins should
each be bypassed to analog ground with 10 μF tantalum as
well as 0.1 μF ceramic capacitors. In a case where the inter-
nally generated reference voltages are not sufficient, the
user may supply external voltages to the reference pins.
However, the reference pin V
REFT
should be within the range
of 2.0V to 2.5V. Similarly, V
should be driven in the
range of 0.4V to 0.9V.Any device used to drive the reference
pins should be able to source adequate current into the
V
and sink adequate current from the V
pin when
the reference resistor ladder is at its minimum resistivity of
850
.
The reference voltage at the top of the resistor ladder
(V
) may be as low as 1.2V above the voltage at the bot-
tom of the resistor ladder (V
) and may be as high as
1.8V above. V
may be as low as 0.4V and as high as
0.9V above ground. However, noise effects will be minimized
and accurate conversions insured when the total reference
voltage is approximately 2.25V and offset from ground by
0.75V.
ANALOG OFFSET DAC REFERENCE BYPASSING
The analog offset DAC reference pins, VREFP and VREFN,
should be capacitively bypassed in the same fashion as the
ADC
reference
pins
VREFT
’Analog-to-Digital Converter Reference Bypassing’).
and
VREFB
(see
DS101292-14
FIGURE 15. PGA Gain (Linear Scale) vs. PGA Gain Code
DS101292-15
FIGURE 16. PGA Gain (Logarithmic Scale) vs. PGA Gain Code
DS101292-16
FIGURE 17. Reference Bypassing
L
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