參數(shù)資料
型號(hào)： LM9833
廠商： National Semiconductor Corporation
英文描述： LM9833 48-Bit Color, 1200dpi USB Image Scanner
中文描述： LM9833 48位彩色，1200dpi的USB圖像掃描儀
文件頁(yè)數(shù)： 8/42頁(yè)
文件大?。?/td> 547K
代理商： LM9833
8
www.national.com
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified.
Note 3:
When the input voltage (V
) at any pin exceeds the power supplies (V
<GND or V
>V
or V
), the current at that pin should be limited to 25mA. The 50mA
maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
max,
Θ
and the ambient temperature, T
. The maximum allow-
able power dissipation at any temperature is P
D
= (T
J
max - T
A
) /
Θ
JA
. T
J
max = 150°C for this device. The typical thermal resistance (
Θ
JA
) of this part when board mounted
is 53°C/W
.
Note 5:
Human body model, 100pF capacitor discharged through a 1.5k
resistor. Machine model, 200pF capacitor discharged through a 0
resistor.
Note 6:
See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear
Data Book for other methods of soldering surface mount devices.
Note 7:
Two diodes clamp the OS analog inputs to
AGND
and
VA
as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the sensor, prevents damage to the LM9833 from transients during power-up.
Note 8:
For best performance, it is required that all supply pins be powered from the same power supply with separate bypass capacitors at each supply pin.
Note 9:
Typicals are at T
J
=T
A
=25°C, f
CRYSTAL IN
= 48MHz, and represent most likely parametric norm.
Note 10:
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11:
Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC.
Note 12:
V
is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. V
is defined as the peak CCD pixel output voltage for
a white (full scale) image with respect to the reference level, V
.
V
is defined as the peak positive deviation above V
of the reset feedthrough pulse. The maximum
correctable range of pixel-to-pixel V
variation is defined as the maximum variation in V
WHITE
(due to PRNU, light source intensity variation, optics, etc.) that the
LM9833 can correct for using its internal PGA.
Note 13:
PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
where
.
GainPGA
V
31
Note 14:
DNL, INL, and Power Supply Current are specified at the 80% Bias Current Setting (Register 9). This is the maximum recommended Bias Current setting, and
gives the best analog performance as well as lower power consumption for USB-bus powered applications.
AC Electrical Characteristics
The following specifications apply for AGND=DGND=0V, V
A
=V
D
=V
DRAM
=+5.0V
DC
unless otherwise noted,
f
CRYSTAL IN
= 48MHz, MCLK DIVIDER = 1.0 (unless otherwise noted), f
MCLK
= f
CRYSTAL IN
/MCLK DIVIDER, f
ADC CLK
= f
MCLK
/8,
C
L
(databus loading) = 20pF/pin.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 8, 9, & 10)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
DRAM Timing (Figure 1)
t
RD SETUP
Data valid to RD rising edge
V
DRAM
=5.0V
V
DRAM
=3.3V
26
35
ns (min)
ns (min)
t
RD HOLD
Data valid after RD rising edge
0
ns (min)
t
WR SETUP
Data valid before WR falling edge
5
ns (min)
t
WR HOLD
Data valid after WR rising edge
10
ns (min)
OS Input
AGND
VA
To Internal
Circuitry
V
WHITE
V
REF
V
RFT
CCD Output Signal
V
---
G0
X--------------------------
+
=
X
G31
G0
–
(
)
32
------
=
L
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