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參數(shù)資料
| 型號(hào)： | LM9811CCVF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 605K |
| 代理商： | LM9811CCVF |
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Applications Information
(Continued)
1.2 The CCD Clocking Signals
To maximize the flexibility of the LM9811, the CCD’s
φ
1,
φ
2,
RS, and TR pulses are internally generated, with a wide
range of options, making these signals compatible with most
commercial linear CCDs. In many cases, these output sig-
nals can drive the CCD clock inputs directly, with only series
resistors (for slew rate control) between the LM9811’s out-
puts and the CCD clock inputs.
1.3 The Digital Interface
There are three main sections to the digital interface of the
LM9811: a serial interface to the Configuration Register,
where all device programming is done, an 8 bit-wide input
databus for gain correction coefficients with a synchronous
clock output (CCLK), and a 10-bit output databus for the final
pixel output data with a synchronous end of conversion out-
put signal (EOC) and an output enable input (RD). Please
note that the CS input affects only the serial I/O–it has no ef-
fect on the output databus, input coefficient bus, or any other
section of the LM9811.
2.0 DIGITAL INTERFACE
2.1 Reading and Writing to the Configuration Register
Communication with the Configuration Register is done
through a standard MICROWIRE
serial interface. This in-
terface is also compatible with the Motorola SPI
standard
and is simple enough to easily be implemented in custom
hardware if needed.
The serial interface timing is shown in Figures 13, 14 and
Figures 16, 17, 18, 19 Data is sent serially, LSB first.
(Please note that some microcontrollers output data MSB
first. When using these microcontrollers the bits in the con-
figuration register are effectively reversed.) Input data is
latched on the rising edge of SCLK, and output data changes
on the falling edge of SCLK. CS must be low to enable serial
I/O.
If SCLK is only clocked when sending or receiving data from
the LM9811, and held low at all other times, then CS can be
tied low permanently as shown in Figures 16, 17, 18, 19 If
SCLK is continuous, then CS must be used to determine the
beginning and the end of a serial byte or word (see Figures
13, 14). Note that CS must make its high-to-low and
low-to-high transitions when SCLK is low, otherwise the in-
ternal bit counter may receive an erroneous pulse, causing
an error in the write or read operation.
Data may be transmitted and received in two 8-bit bytes
(typical with microcontroller interfaces) or one 16-bit word
(for custom serial controllers).
The Configuration Register is programmed by sending a
control byte to the serial port. This byte indicates whether
this is a read or a write operation, and gives the 3-bit address
of the register bank to be read from or written to. If this is a
read operation, the next 8 SCLKs will output the data at the
requested location on the SDO pin. If this is a write opera-
tion, the data to be sent to the specified location should be
clocked in on the SDI input during the next 8 SCLKs. Data is
sent and received using the LSB (Least Significant Bit) first
format.
For maximum system reliability, each configuration register
location can be read back and verified after a write.
If the serial I/O to the configuration register falls out of sync
for any reason, it can be reset by sending 8 or more SCLKs
with CS held high.
2.2 Writing Correction Coefficient Data on the
CD0–CD7 Bus
Correction coefficient data for each pixel is latched on the
rising edge of the CCLK output signal (see Figure 10). Note
that there is a 3 pixel latency between when the coefficient
data is latched and when the output data is available.As Fig-
ure 2 Pixel Pipeline Timing Overviewshows, coefficient data
for pixel n is latched shortly before the output data for pixel
n-2 becomes available on the output databus (DD0–DD9).
Note that there is no way to provide a correction coefficient
for pixel 1, the first pixel in the CCD array. This is usually not
a problem since the first several pixels of a CCD are usually
optical black pixels, and used for clamping.
2.3 Reading Output Data on the DD0–DD9 Bus
The corrected digital output data representing each pixel is
available on the DD0–DD9 databus. The data is valid after
the falling edge of the EOC output. The RD input takes the
databus in and out of TRI-STATE. RD can be held low at all
times if there are no other devices needing the bus, or it can
be used to TRI-STATE the bus between pixels, allowing
other devices access to the bus. Figure 12 Data Timing
(Output and Coefficient Data Sharing Same Bus) shows
how EOC can be tied to RD to automatically multiplex be-
tween coefficient data and conversion data.
2.4 MCLK
This is the master clock input that controls the LM9811. The
pixel conversion rate is fixed at 1/8 of this frequency. Many of
the timing parameters are also relative to the frequency of
this clock.
2.5 SYNC
This input signals the beginning of a line. When SYNC goes
high, the LM9811 generates a TR pulse, then begins con-
verting pixels until the SYNC line is brought low again. Since
there is no pixel counter in the LM9811, it will work with
CCDs of any length.
3.0 DIGITAL CCD INTERFACE
3.1 Buffering
φ
1,
φ
2, RS, and TR
The LM9811 can drive the
φ
1,
φ
2, RS, and TR inputs of many
CCDs directly, without the need for external buffers between
the LM9811 and the CCD. Most linear CCDs designed for
scanner applications require 0V to 5V signal swings into
20pF to 500pF input loading. Series resistors are typically in-
serted between the driver and the CCD to control slew rate
and isolate the driver from the large load capacitances. The
values of these resistors are usually given in the CCD’s
datasheet.
4.0 ANALOG INTERFACE
4.1 Voltage Reference
The two REF IN pins should be connected to a 1.225V
±
2%
reference voltage capable of sinking between 2 mA and
5 mA of current coming from the 500
–1400
resistor string
between REF OUT
and REF IN. The LM4041-1.2 1.225V
bandgap reference is recommended for this application as
shown in Figure 21 The inexpensive “E” grade meets all the
www.national.com
22
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| LM9831CCVJD | LM9831 42-Bit Color, 1200dpi USB Image Scanner |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM9812 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9812 30-Bit Color Linear CCD Sensor Processor |
| LM9812CCV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9812 30-Bit Color Linear CCD Sensor Processor |
| LM981-SC36 | 功能描述:基本/快動(dòng)開關(guān) Foot Switch RoHS:否 制造商:Omron Electronics 觸點(diǎn)形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級(jí):IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
| LM981-ZZ | 功能描述:基本/快動(dòng)開關(guān) Foot Switch RoHS:否 制造商:Omron Electronics 觸點(diǎn)形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級(jí):IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
| LM981-ZZ-1 | 功能描述:基本/快動(dòng)開關(guān) Foot Switch RoHS:否 制造商:Omron Electronics 觸點(diǎn)形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級(jí):IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
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