參數(shù)資料
型號: LM9071T
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Low-Dropout System Voltage Regulator with Delayed Reset
中文描述: 5 V FIXED POSITIVE LDO REGULATOR, 0.8 V DROPOUT, PSFM5
封裝: PLASTIC, TO-220, 5 PIN
文件頁數(shù): 5/7頁
文件大?。?/td> 193K
代理商: LM9071T
Application Hints
The LM9071 voltage regulator has been optimized for use in
microprocessor based automotive systems. Several unique
design features have been incorporated to address many
FMEA (Failure Mode Effects Analysis) concerns for fail-safe
system performance.
FAULT TOLERANT FEATURES
While not specifically guaranteed due to production testing
limitations, the LM9071 has been tested and shown to con-
tinue to provide a regulated output and, not generate an er-
roneous system reset signal while subjected to high levels of
RF electric field energy (up to 300 V/m signal strength over
a 2 MHz to 400 MHz frequency range). This is very important
in vehicle safety related applications where the system must
continue to operate normally. To maintain this immunity to
RFI the output bypass capacitor is important (47 μF is rec-
ommended).
An output bypass capacitor of at least 10 μF is required for
stability (47 μF is recommended). The ESR of this capacitor
should be less than 3
. An input capacitor of 1 μF or larger
is recommended to improve line transient and noise perfor-
mance.
Conventional load dump protection is built in to withstand up
to +60V and 50V transients. Protection against reverse po-
larity battery connections is also built in. With a reversed bat-
tery connection the output of the LM9071 will not go more
negative than one diode drop below ground. This will prevent
damage to any of the 5V load circuits.
RESET FLAG
Excessive loading of the output to the point where the output
voltage drops by 300 mV to 500 mV will signal a reset flag to
the micro. This will warn of a V
supply that may produce
unpredictable operation of the system. On power-up and re-
covery from a fault condition the delay capacitor is used to
hold the micro in a reset condition for a programmable time
interval to allow the system operating voltages and clock to
stabilize before executing code. The delay time interval can
be estimated by the following equation:
INPUT STABILITY
Low dropout voltage regulators which utilize a PNP power
transistor usually exhibit a large increase in current when in
dropout (V
<
5.5V). This increase is caused by the satura-
tion characteristics (
β
reduction) of the PNP transistor. To
significantly minimize this increase in current the LM9071
detects when the PNP enters saturation and reduces the op-
erating current.
This reduction in input current can create a stability problem
in applications with higher load current (
>
100 mA) where
the input voltage is applied through a long length of wire,
which in effect adds a significant amount of inductance in se-
ries with the input. The drop in input current may create a
positive input voltage transient which may take the PNP out
of saturation. If the input voltage is held constant at the
threshold where the PNP is going in and out of saturation, an
oscillation may be created.
This is only observed where a large series inductance is
present in the input supply line and when the rise and fall
time of the input supply is very slow. If the application and re-
moval of the input voltage changes at a rate greater than
500 mV/μs it will move through the dropout region of the
regulator (V
of 3V to 5.5V) too quickly for an oscillation to
be established.
L
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