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參數(shù)資料
| 型號(hào)： | LM8261M5 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | RRIO, High Output Current & Unlimited Cap Load Op Amp in SOT23-5 |
| 中文描述： | OP-AMP, 9000 uV OFFSET-MAX, 24 MHz BAND WIDTH, PDSO5 |
| 封裝： | SOT-23, 5 PIN |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 915K |
| 代理商： | LM8261M5 |
Application Notes:
Block Diagram and Operational Description:
A) Input Stage:
As can be seen from the simplified schematic in Figure 1 the
input stage consists of two distinct differential pairs (Q1-Q2
and Q3-Q4) in order to accommodate the full Rail-to-Rail in-
put common mode voltage range. The voltage drop across
R5, R6, R7, and R8 is kept to less than 200mV in order to al-
low the input to exceed the supply rails. Q13 acts as a switch
to steer current away from Q3-Q4 and into Q1-Q2, as the in-
put increases beyond 1.4V of V
+
. This in turn shifts the signal
path from the bottom stage differential pair to the top one
and causes a subsequent increase in the supply current.
In transitioning from one stage to another, certain input stage
parameters (V
, I
, I
, e
, and i
) are determined based on
which differential pair is
″
on
″
at the time. Input Bias current,
I
, will change in value and polarity as the input crosses the
transition region. In addition, parameters such as PSRR and
CMRR which involve the input offset voltage will also be ef-
fected by changes in V
CM
across the differential pair transi-
tion region.
The input stage is protected with the combination of R9-R10
and
D1,
D2,
D3,
and
D4
over-voltages. This fault condition could otherwise harm the
differential pairs or cause offset voltage shift in case of pro-
longed over voltage. As shown in Figure 2 if this voltage
reaches approximately +/1.4V at 25C, the diodes turn on
and current flow is limited by the internal series resistors (R9
and R10). TheAbsolute Maximum Rating of +/10V differen-
tial on V
still needs to be observed. With temperature varia-
tion, the point were the diodes turn on will change at the rate
of 5mV/C.
against
differential
input
B) Output Stage:
The output stage Figure 1 is comprised of complementary
NPN and PNP common-emitter stages to permit voltage
swing to within a V
of either supply rail. Q9 supplies the
sourcing and Q10 supplies the sinking current load. Output
current limiting is achieved by limiting the V
of Q9 and Q10;
using this approach to current limiting, alleviates the draw
back to the conventional scheme which requires one V
be
re-
duction in output swing.
The frequency compensation circuit includes Miller capaci-
tors from collector to base of each output transistor (see Fig-
ure 1 C
and C
). At light capacitive loads, the
high frequency gain of the output transistors is high, and the
Miller effect increases the effective value of the capacitors
thereby stabilizing the Op Amp. Large capacitive loads
greatly decrease the high frequency gain of the output tran-
sistors thus lowering the effective internal Miller capacitance
- the internal pole frequency increases at the same time a
low frequency pole is created at the Op Amp output due to
the large load capacitor. In this fashion, the internal dominant
pole compensation, which works by reducing the loop gain to
less than 0dB when the phase shift around the feedback
loop is more than 180C, varies with the amount of capaci-
tive load and becomes less dominant when the load capaci-
tor has increased enough. Hence the Op Amp is very stable
even at high values of load capacitance resulting in the un-
characteristic feature of stability under all capacitive loads.
Driving Capacitive Loads:
The LM8261 is specifically designed to drive unlimited ca-
pacitive loads without oscillations (See Settling Time and
Percent Overshoot vs. Cap Load plots in the typical perfor-
mance characteristics section). In addition, the output cur-
rent handling capability of the device allows for good slewing
characteristics even with large capacitive loads (see Slew
Rate vs. Cap Load plots). The combination of these features
is ideal for applications such as TFT flat panel buffers, A/D
converter input amplifiers, etc.
However, as in most Op Amps, addition of a series isolation
resistor between the Op Amp and the capacitive load im-
proves the settling and overshoot performance.
Output current drive is an important parameter when driving
capacitive loads. This parameter will determine how fast the
output voltage can change. Referring to the Slew Rate vs.
Cap Load Plots (typical performance characteristics sec-
tion), two distinct regions can be identified. Below about
10,000pF, the output Slew Rate is solely determined by the
DS101084-67
FIGURE 1. Simplified schematic Diagram
DS101084-66
FIGURE 2. Input Stage Current vs Differential Input
Voltage
L
www.national.com
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM8261M5 | 制造商:Texas Instruments 功能描述:OP AMP HIGH O/P RRI/O SMD 8261 |
| LM8261M5/NOPB | 功能描述:運(yùn)算放大器 - 運(yùn)放 RRIO,Hi Out Crnt & UnLtd Cap Load OpAmp RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LM8261M5/NOPB | 制造商:Texas Instruments 功能描述:Operational Amplifier (Op-Amp) IC |
| LM8261M5NOPB | 制造商:Texas Instruments 功能描述:OP Amp Single GP R-R I/O ±15V/30V 5-Pin SOT-23 T/R |
| LM8261M5X | 功能描述:運(yùn)算放大器 - 運(yùn)放 RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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