參數(shù)資料
型號: LM81CIMT-3
英文描述: DATA ACQ SYSTEM|6-CHANNEL|8-BIT|TSSOP|24PIN|PLASTIC
中文描述: 數(shù)據(jù)ACQ木材系統(tǒng)| 6聲道| 8位| TSSOP封裝| 24針|塑料
文件頁數(shù): 28/33頁
文件大小: 388K
代理商: LM81CIMT-3
Functional Description
(Continued)
13.7 Interrupt Mask Register 2—Address 44h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
Name
Read/
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
0
1
2
3
4
5
6
7
+12Vin
Vccp2
Reserved
Reserved
Chassis Intrusion
Reserved
Reserved
RESET Enable
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
<
7
>
= 1 in INT Mask Register 2 enables the RESET in the Configuration Register.
13.8 Reserved Register —Address 45h
Power on default –
<
7:0
>
= 00h. Read/Write for backwards compatibility.
13.9 CI Clear Register—Address 46h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
Name
Read/
Write
Read/Write
Read/Write
Description
0-6
Reserved
CI Clear
7
A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The
register bit self clears after the pulse has been output. This bit is mirrored in
Configuration Register bit 6.
L
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相關(guān)PDF資料
PDF描述
LM81BIMT-3 DATA ACQ SYSTEM|6-CHANNEL|8-BIT|TSSOP|24PIN|PLASTIC
LM81BIMTX-3 DATA ACQ SYSTEM|6-CHANNEL|8-BIT|TSSOP|24PIN|PLASTIC
LM81CIMTX-3 Single-Ended Data Acquisition System
LM8362_SERIES
LM8363_SERIES
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