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參數(shù)資料
| 型號(hào)： | LM81CIMT-31 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Serial Interface ACPI-Compatible Microprocessor System |
| 中文描述： | 串行接口ACPI的兼容微處理器系統(tǒng) |
| 文件頁數(shù)： | 25/32頁 |
| 文件大?。?/td> | 412K |
| 代理商： | LM81CIMT-31 |
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Functional Description
(Continued)
13.3 Configuration Register— Address 40h
Power on default –
<
7:0
>
= 00001000 binary
Bit
Name
Read/
Write
Read/Write
Description
0
Start
A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note:
The outputs of Interrupt pins will not be cleared if the user writes a zero to this
location after an interrupt has occurred unlike “INT_Clear” bit.
At start up, limit checking functions and scanning begin. Note, all limits should be set
in the Value RAM before setting this bit HIGH.
A one enables the INT Interrupt output.
1
2
3
INT Enable
Reserved
INT_Clear
Read/Write
Read/Write
Read/Write
A one disables the INT output without affecting the contents of Interrupt Status
Registers. The device will stop monitoring. It will resume upon clearing of this bit.
A one outputs at least a 20 ms active low reset signal at RESET. This bit is cleared
once the pulse has gone inactive.
4
RESET
Read/Write
5
6
Reserved
CI_Clear
Read/Write
Read/Write
A one outputs a minimum 20 ms active low pulse on the CI pin. The register bit self
clears after the pulse has been output. This bit is mirrored in the CI Clear Register bit
7.
A one restores power on default value to the Configuration Register, Interrupt Status
Registers, Interrupt Mask Registers, CI Clear Register, VID/Fan Divisor Register,
VID4, Temperature Configuration Register, and the Extended Mode Registers. This bit
clears itself since the power on default is zero.
7
INITIALIZATION
Read/Write
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