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參數(shù)資料
| 型號(hào)： | LM79 |
| 文件頁(yè)數(shù)： | 8/31頁(yè) |
| 文件大?。?/td> | 481K |
| 代理商： | LM79 |
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AC Electrical Characteristics
(Note 13) The following specifications apply for +4.25 V
DC
≤
V
CC
≤
+5.75 V
DC
unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
=
25C. (Continued)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
ISA READ TIMING
t
SDRD
(setup)
t
SDRD
(hold)
t
RD
(setup)
t
RS
(delay)
Data Valid to IORD Inactive
IORD Inactive to Data Invalid
IORD Active to Rising Edge of SYSCLK
Rising Edge of SYSCLK number 1 to Data
Valid
120
5
20
360
ns (min)
ns (min)
ns (min)
ns (max)
With 8.33 MHz
SYSCLK
DS100036-5
The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that a Power-on reset does not
occur unintentionally. (See Section 3.2 ‘Resets’ )
FIGURE 2. ISA Bus Read Timing Diagram
L
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8
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