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參數(shù)資料
| 型號(hào)： | LM76CNMX-3 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | 【0.5∑C, 【1∑C, 12-Bit Sign Digital Temperature Sensor and Thermal Window Comparator with Two-Wire Interface |
| 中文描述： | DIGITAL TEMP SENSOR-SERIAL, 13BIT(s), 1Cel, RECTANGULAR, SURFACE MOUNT |
| 封裝： | 0.150 INCH, PLASTIC, SO-8 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 311K |
| 代理商： | LM76CNMX-3 |
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Logic Electrical Characteristics
(Continued)
DIGITAL DC CHARACTERISTICS
Unless otherwise noted, these specifications apply for for +V
=+3.3 Vdc
±
5% for the
LM76CNM-3 and for +V
=+5.0 Vdc
±
10% for the LM76CHM-5. .
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all
other limits T
A
= T
J
=+25C, unless otherwise noted.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
0.3
Units
(Limit)
V (min)
V
IN(0)
SDA and SCL Logical “0” Input
Voltage
+V
S
x 0.3
250
V (max)
mV (min)
V
IN(HYST)
SDA and SCL Digital Input
Hysteresis
A0 and A1 Logical “1” Input
Voltage
500
V
IN(1)
2.0
V (min)
+V
S
+0.3
0.3
V (max)
V (min)
V
IN(0)
A0 and A1 Logical “0” Input
Voltage
0.8
1.0
1.0
V (max)
μA (max)
μA (max)
pF
μA (max)
V (max)
V (max)
I
IN(1)
I
IN(0)
C
IN
I
OH
V
OL
Logical “1” Input Current
Logical “0” Input Current
Capacitance of All Digital Inputs
High Level Output Current
Low Level Output Voltage
T_CRIT_A Output Saturation
Voltage
T_CRIT_A Delay
V
IN
= + V
S
V
IN
= 0V
0.005
0.005
20
V
OH
= + V
S
I
OL
= 3 mA
I
OUT
= 4.0 mA
(Note 12)
10
0.4
0.8
1
Conversions
(max)
ns (max)
t
OF
Output Fall Time
C
L
= 400 pF
I
O
= 3 mA
250
SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS
Unless otherwise noted, these specifications apply for +V
=+3.3
Vdc
±
5% for the LM76CNM-3 and for +V
=+5.0 Vdc
±
10% for the LM76CHM-5, CL (load capacitance) on output lines = 80
pF unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25C, unless oth-
erwise noted.
The switching characteristics of the LM76 fully meet or exceed the published specifications of the I
2
C bus. The following pa-
rameters are the timing relationship between SCL and SDA signal related to the LM76. They are not the I
2
C bus specifica-
tions.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
2.5
100
0
100
100
Units
(Limit)
μs(min)
ns(min)
ns(min)
ns(min)
ns(min)
t
1
t
2
t
3
t
4
t
5
SCL (Clock) Period
Data in Set-Up Time to SCL High
Data Out Stable after SCL Low
SDA Low Set-Up Time to SCL Low (Start Condition)
SDA High Hold Time after SCL High (Stop Condition)
DS101015-4
L
www.national.com
5
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