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參數(shù)資料
| 型號(hào)： | LM76CNM-3 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | 【0.5∑C, 【1∑C, 12-Bit Sign Digital Temperature Sensor and Thermal Window Comparator with Two-Wire Interface |
| 中文描述： | DIGITAL TEMP SENSOR-SERIAL, 13BIT(s), 1Cel, RECTANGULAR, SURFACE MOUNT |
| 封裝： | 0.150 INCH, PLASTIC, SO-8 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 311K |
| 代理商： | LM76CNM-3 |
1.0 Functional Description
(Continued)
1.9 POINTER REGISTER
(Selects which registers will be read from or written to):
P7
0
P6
0
P5
0
P4
0
P3
0
P2
P1
P0
Register Select
P0–P2: Register Select:
P2
0
P1
0
P0
0
Register
Temperature (Read only) (Power-up
default)
Configuration (Read/Write)
T
HYST
(Read/Write)
T_CRIT (Read/Write)
T
LOW
(Read/Write)
T
HIGH
(Read/Write)
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
P3–P7: Must be kept zero.
1.10 TEMPERATURE REGISTER
(Read Only):
D15
D14
Sign
MSB
D13
Bit
10
D12
Bit 9
D11
Bit 8
D10
Bit 7
D9
Bit 6
D8
Bit 5
D7
Bit 4
D6
Bit 3
D5
Bit 2
D4
Bit 1
D3
Bit 0
D2
D1
D0
CRIT
HIGH
LOW
Status Bits
D0–D2: Status Bits
D3–D15: Temperature Data. One LSB = 0.0625C. Two’s complement format.
1.11 CONFIGURATION REGISTER
(Read/Write):
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
Fault Queue
INT Polarity
T_CRIT_A
Polarity
INT Mode
Shutdown
D0: Shutdown - When set to 1 the LM76 goes to low power shutdown mode. Power up default of “0”.
D1: Interrupt mode - 0 is Comparator Interrupt mode, 1 is Event Interrupt mode. Power up default of “0”.
D2, D3: T_CRIT_A and INT Polarity - 0 is active low, 1 is active high. Outputs are open-drain. Power up default of “0”
D4: Fault Queue - When set to 1 the Fault Queu is enabled,
see Section 1.7 Power up default of “0”.
D5–D7: These bits are used for production testing and must be kept zero for normal operation.
1.12 T
HYST
, T
LOW
, T
HIGH
AND T_CRIT_A REGISTERS
(Read/Write):
D15
D14
D13
D12
Sign
MSB
Bit
10
D0–D2: Undefined
D3–D15: T
, T
LOW
, T
HIGH
or T_CRITTrip Temperature Data. Power up default is T
LOW
=10C, T
HIGH
=64C, T_CRIT=80C,
T
HYST
= 2C.
T
HYST
is subtracted from T
HIGH
, and T_CRIT, and added to T
LOW
.
Avoid programming setpoints so close that their hysteresis values overlap. See Section 1.1
D11
Bit 8
D10
Bit7
D9
Bit6
D8
Bit5
D7
Bit 4
D6
Bit 3
D5
Bit 2
D4
Bit 1
D3
Bit 0
D2
X
D1
X
D0
X
Bit 9
L
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