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參數(shù)資料
| 型號(hào)： | LM64CILQ-F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | UART W/16BYTE TX/RX FIFO |
| 中文描述： | 【1ΣC遠(yuǎn)程二極管溫度傳感器，PWM風(fēng)扇控制和5個(gè)GPIO的 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 376K |
| 代理商： | LM64CILQ-F |
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Notes
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise noted.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supplies (V
IN
<
GND or V
IN
>
V+), the current at that pin should be limited to 5 mA. Parasitic
components and/or ESD protection circuitry are shown in the table below, for the LM64’s pins, by an "X" when it exists. Care should be taken not to forward bias
the parasitic diode, D1, present on pins D+ and D. Doing so by more than 50 mV may corrupt temperature measurements.
Pin Name
GPIO1
GPIO2
GPIO3
PWM
V
DD
D+
D
T_Crit
A0
ALERT
TACH
SMBDAT
SMBCLK
GPIO5
GPIO4
GPD1
GPD2
GPD3
GPD4
GPD5
PIN
#
1
2
3
4
5
6
7
8
12
14
15
16
17
18
19
20
21
22
23
24
D1
D2
D3
D4
D5
D6
X
X
X
X
R1
X
X
X
X
SNP
X
X
X
X
ESD CLAMP
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Note 4:
Human body model, 100 pF discharged through a 1.5 k
resistor. Machine model, 200 pF discharged directly into each pin. See Figure 2 above for the ESD
Protection Input Structure.
Note 5:
See the National Semiconductor Application Note AN-1187 for Thermal Resistance Junction-to-Ambient Temperature.
Note 6:
See the National Semiconductor Application Note AN-1187 for recommendations on SMT assembly using the LLP packages.
Note 7:
“Typicals” are at T
A
= 25C and represent most likely parametric norm. They are to be used as general reference values not for critical design calculations.
Note 8:
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9:
The supply current will not increase substantially with an SMBus transaction.
Note 10:
Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the internal power
dissipation of the LM64 and the thermal resistance. See (Note 5) for the thermal resistance to be used in the self-heating calculation.
Note 11:
The output rise time is measured from (V
IL max
- 0.15 V) to (V
IH min
+ 0.15 V).
Note 12:
The output fall time is measured from (V
IH min
+ 0.15 V) to (V
IL min
- 0.15 V).
Note 13:
Holding the SMBData and/or SMBCLK lines Low for a time interval greater than t
TIMEOUT
will reset the LM64’s SMBus state machine, therefore setting
SMBDAT and SMBCLK pins to a high impedance state.
20065505
FIGURE 2. ESD Protection Input Structure
L
www.national.com
8
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