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參數(shù)資料
| 型號： | LM64 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | 【1∑C Remote Diode Temperature Sensor with PWM Fan Control and 5 GPIO’s |
| 中文描述： | 【1ΣC遠(yuǎn)程二極管溫度傳感器，PWM風(fēng)扇控制和5個GPIO的 |
| 文件頁數(shù)： | 7/29頁 |
| 文件大?。?/td> | 363K |
| 代理商： | LM64 |
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SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
DD
= +3.0 VDC to +3.6 VDC, C
L
(load capacitance) on output lines =
80 pF.
Boldface limits apply for T
A
= T
J
; T
MIN
≤
T
A
≤
T
MAX
;
all other limits T
A
= T
J
= +25C, unless otherwise noted. The
switching characteristics of the LM64 fully meet or exceed the published specifications of the SMBus version 2.0. The following
parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM64. They adhere to but are
not necessarily the same as the SMBus bus specifications.
Symbol
Parameter
Conditions
Limits
(Note 8)
10
100
4.7
4.0
50
1
0.3
250
25
35
250
300
930
Units
(Limit)
kHz (min)
kHz (max)
μs (min)
μs (min)
μs (max)
μs (max)
μs (max)
ns (max)
ms (min)
ms (max)
ns (min)
ns (min)
ns (max)
f
SMB
SMBus Clock Frequency
t
LOW
t
HIGH
SMBus Clock Low Time
SMBus Clock High Time
From V
IN(0) max
to V
IN(0) max
From V
IN(1) min
to V
IN(1) min
t
R
t
F
t
OF
t
TIMEOUT
SMBus Rise Time
SMBus Fall Time
Output Fall Time
SMBData and SMBCLK Time Low for Reset
of Serial Interface See (Note 13)
Data In Setup Time to SMBCLK High
Data Out Hold Time after SMBCLK Low
(Note 11)
(Note 12)
C
L
= 400 pF, I
O
= 3 mA
t
SU:DAT
t
HD:DAT
t
HD:STA
Hold Time after (Repeated) Start Condition.
After this period the first clock is generated.
Stop Condition SMBCLK High to SMBDAT
Low (Stop Condition Setup)
SMBus Repeated Start-Condition Setup Time,
SMBCLK High to SMBDAT Low
SMBus Free Time between Stop and Start
Conditions
4.0
μs (min)
t
SU:STO
100
ns (min)
t
SU:STA
4.7
μs (min)
t
BUF
4.7
μs (min)
20065504
FIGURE 1. SMBus Timing Diagram for SMBCLK and SMBDAT Signals
L
www.national.com
7
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