參數(shù)資料
型號: LM6211MF
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運動控制電子
英文描述: Low Noise, RRO Operational Amplifier with CMOS Input and 24V Operation
中文描述: OP-AMP, 2800 uV OFFSET-MAX, 17 MHz BAND WIDTH, PDSO5
封裝: SOT-23, 5 PIN
文件頁數(shù): 12/19頁
文件大小: 1091K
代理商: LM6211MF
Application Notes
(Continued)
In the Loop Compensation
Figure 2
illustrates a compensation technique, known as ‘in
the loop’ compensation, that employs an RC feedback circuit
within the feedback loop to stabilize a non-inverting amplifier
configuration. A small series resistance, R
, is used to iso-
late the amplifier output from the load capacitance, C
L
, and a
small capacitance, C
F
, is inserted across the feedback re-
sistor to bypass C
L
at higher frequencies.
The values for R
and C
are decided by ensuring that the
zero attributed to C
lies at the same frequency as the pole
attributed to C
. This ensures that the effect of the second
pole on the transfer function is compensated for by the
presence of the zero, and that the ROC is maintained at
20 dB/decade. For the circuit shown in
Figure 2
the values of
R
and C
are given by
Equation (1)
.
Table 1
shows different
values of R
and C
that need to be used for maintaining
stability with different values of C
L
, as well as the phase
margins to be expected. R
and R
IN
are assumed to be 10
k
, R
L
is taken as 2 k
, while R
OUT
is taken to be 60
.
(1)
TABLE 1.
C
L
(pF)
250
300
500
R
S
(
)
60
60
60
C
F
(pF)
4.5
5.4
9
Phase Margin ()
39.8
49.5
53.1
Although this methodology provides circuit stability for any
load capacitance, it does so at the price of bandwidth. The
closed loop bandwidth of the circuit is now limited by R
S
and
C
F
.
Compensation by External Resistor
In some applications it is essential to drive a capacitive load
without sacrificing bandwidth. In such a case, in the loop
compensation is not viable. A simpler scheme for compen-
sation is shown in
Figure 3
. A resistor, R
, is placed in
series between the load capacitance and the output. This
introduces a zero in the circuit transfer function, which coun-
teracts the effect of the pole formed by the load capacitance,
and ensures stability.
The value of R
ISO
to be used should be decided depending
on the size of C
L
and the level of performance desired.
Values ranging from 5
to 50
are usually sufficient to
ensure stability. A larger value of R
ISO
will result in a system
with lesser ringing and overshoot, but will also limit the
output swing and the short circuit current of the circuit.
Stability and Input Capacitance
In certain applications, for example I-V conversion, transim-
pedance photodiode amplification and buffering the output of
current-output DAC, capacitive loading at the input of the op
amp can endanger stability. The capacitance of the source
driving the op amp, the op amp input capacitance and the
parasitic/wiring capacitance contribute to the loading of the
input. This capacitance, C
, interacts with the feedback
network to introduce a peaking in the closed loop gain of the
circuit, and hence causes instability.
This peaking can be eliminated by adding a feedback ca-
pacitance, C
F
, as shown in
Figure 4
. This introduces a zero
in the feedback network, and hence a pole in the closed loop
response, and thus maintains stability. An optimal value of
C
F
is given by
Equation (2)
. A simpler approach is to select
C
F
= (R
1
/R
2
)C
IN
for a 90 phase margin. This approach,
however, limits the bandwidth excessively.
20120338
FIGURE 2. In the Loop Compensation
20120356
FIGURE 3. Compensation By Isolation Resistor
20120349
FIGURE 4. Compensating for Input Capacitance
L
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