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Applications Information
(Continued)
The time t2 provides a periodic cool-down time for the power
converter in the event of a sustained overload or short
circuit. This results in lower average input current and lower
power dissipated within the power components. It is recom-
mended that the ratio of t2/(t1 + t3) be in the range of 5 to 10
to make good use of this feature. If the application requires
no delay from the first detection of a current limit condition to
the onset of the hiccup mode (t1 = 0), the RES pin can be left
open (no external capacitor). If it is desired to disable the
hiccup mode current limit operation, the RES pin should be
connected to ground (AGND).
SOFT-START (SS)
An internal current source and an external soft-start capaci-
tor determines the time required for the output duty cycle to
increase from zero to its final value for regulation. The mini-
mum acceptable time is dependent on the output capaci-
tance and the response of the feedback loop. If the soft-start
time is too quick, the output could overshoot its intended
voltage before the feedback loop can regulate the PWM
controller. After power is applied and the controller is fully
enabled, the voltage at the SS pin ramps up as C
is
charged by an internal 50 μA current source. The voltage at
the output of the COMP pin current mirror is clamped to the
same potential as the SS pin by a voltage buffer with a
sink-only output stage. When the SS voltage reaches
≈
1.4V,
PWM pulses appear at the driver output with very low duty
cycle. The PWM duty cycle gradually increases as the volt-
age at the SS pin charges to
≈
5.0V.
VOLTAGE DEPENDENT MAXIMUM DUTY CYCLE
As the input source V
increases the voltage at the UVLO
pin increases proportionately. To limit the Volt x Seconds
applied to the transformer, the maximum allowed PWM duty
cycle decreases as the UVLO voltage increases. If it is
desired to increase the slope of the voltage limited duty cycle
characteristic, two possible configurations are shown in
Fig-
ure 17
. After the LM5026 is enabled, the zener diode causes
the UVLO pin voltage to increase more rapidly with increas-
ing input voltage (V
). The voltage dependent maximum
duty cycle clamp varies with the UVLO pin voltage according
to the following equation:
Voltage-Dependent Duty Cycle (%) = 107 - 21.8 X UVLO
Programmable Maximum Duty Cycle Clamp (DCL)
When the UVLO pin is biased at 1.25V (minimum operating
level), the maximum duty cycle of OUT_A is limited by the
duty cycle of the internal clock signal. The duty cycle of the
internal clock can be adjusted by programming a voltage set
at the DCL pin. The default maximum duty cycle (80%) can
be selected by connecting the DCL pin to the RT pin. The
DCL pin should not be left open. A small decoupling capaci-
tor located close to the DCL pin is recommended.
The oscillator frequency set resistance (R
) must be deter-
mined first before programming the maximum duty cycle.
Following the selection of the total R
resistance, the ratio of
the R
resistors can be designed to set the desired maxi-
mum duty cycle. As the UVLO pin voltage increases from
1.25V, the maximum duty cycle is reduced by the voltage
dependent duty cycle limiter previously as described and
illustrated in
Figure 6
.
Printed Circuit Board Layout
The LM5026 Current Sense and PWM comparators are very
fast, and respond to short duration noise pulses. The com-
ponents at the CS, COMP, SS, DCL, UVLO, TIME, SYNC
20147931
FIGURE 17. Altering the Slope of Duty Cycle vs. V
PWR
L
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