參數(shù)資料
型號(hào): LM5025AMTC
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Active Clamp Voltage Mode PWM Controller
中文描述: 3 A SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO16
封裝: TSSOP-16
文件頁(yè)數(shù): 3/16頁(yè)
文件大小: 698K
代理商: LM5025AMTC
Pin Description
(Continued)
PIN
8
NAME
OUT_A
DESCRIPTION
APPLICATION INFORMATION
Output of the main switch PWM output gate driver.
Output capability of 3A peak sink current.
Output of the Active Clamp switch gate driver.
Capable of 1.25A peak sink current..
Connect directly to analog ground.
Connect directly to power ground. For the LLP
package option the exposed pad is electrically
connected to AGND.
An external capacitor and an internal 20μA current
source set the softstart ramp. The SS current source
is reduced to 1uA initially following a CS2
over-current event or an over temperature event.
An internal 5K
resistor pull-up is provided on this
pin. The external opto-coupler sinks current from
COMP to control the PWM duty cycle.
An external resistor connected from RT to ground
sets the internal oscillator frequency.
The internal oscillator can be synchronized to an
external clock with a frequency 20% lower than the
internal oscillator’s free running frequency. There is
no constraint on the maximum sync frequency.
An external voltage divider from the power source
sets the shutdown comparator levels. The
comparator threshold is 2.5V. Hysteresis is set by an
internal current source (20μA) that is switched on or
off as the UVLO pin potential crosses the 2.5V
threshold.
Internally bonded to the die substrate. Connect to
GND potential for low thermal impedance.
Main output driver
9
OUT_B
Active Clamp output driver
10
11
PGND
AGND
Power ground
Analog ground
12
SS
Soft-start control
13
COMP
Input to the Pulse Width Modulator
14
RT
Oscillator timing resistor pin
15
SYNC
Oscillator UP/DOWN synchronization input
16
UVLO
Line Under-Voltage shutdown
-
EP
Exposed PAD, underside of the LLP package
option
L
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