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參數(shù)資料
| 型號： | LM5000-3MTCX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.7 A SWITCHING REGULATOR, 840 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 388K |
| 代理商： | LM5000-3MTCX/NOPB |
where R
O is the output impedance of the error amplifier,
850k
. Since R
C is generally much less than RO, it does not
have much effect on the above equation and can be neglected
until a value is chosen to set the zero f
ZC. fZC is created to
cancel out the pole created by the output capacitor, f
P1. The
output capacitor pole will shift with different load currents as
shown by the equation, so setting the zero is not exact. De-
termine the range of f
P1 over the expected loads and then set
the zero f
ZC to a point approximately in the middle. The fre-
quency of this zero is determined by:
Now R
C can be chosen with the selected value for CC. Check
to make sure that the pole f
PC is still in the 10Hz to 100Hz
range, change each value slightly if needed to ensure both
component values are in the recommended range. After
checking the design at the end of this section, these values
can be changed a little more to optimize performance if de-
sired. This is best done in the lab on a bench, checking the
load step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of
R
C (within the range of values) should be chosen. This will
improve the overall bandwidth which makes the regulator re-
spond more quickly to transients. If more detail is required, or
the most optimal performance is desired, refer to a more in
depth discussion of compensating current mode DC/DC
switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just
to improve the overall phase margin of the control loop, an-
other pole may be introduced to cancel the zero created by
the ESR. This is accomplished by adding another capacitor,
C
C2, directly from the compensation pin VC to ground, in par-
allel with the series combination of R
C and CC. The pole
should be placed at the same frequency as f
Z1, the ESR zero.
The equation for this pole follows:
To ensure this equation is valid, and that C
C2 can be used
without negatively impacting the effects of R
C and CC, fPC2
must be greater than 10f
PC.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a band-
width of or less of the frequency of the RHP zero. This is
done by calculating the open-loop DC gain, A
DC. After this
value is known, you can calculate the crossover visually by
placing a 20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is at less than the RHP zero, the phase
margin should be high enough for stability. The phase margin
can also be improved some by adding C
C2 as discussed ear-
lier in the section. The equation for A
DC is given below with
additional equations required for the calculation:
mc
0.072fs (in A/s)
where R
L is the minimum load resistance, VIN is the maximum
input voltage, and R
DSON is the value chosen from the graph
"R
DSON vs. VIN " in the Typical Performance Characteristics
section.
SWITCH VOLTAGE LIMITS
In a flyback regulator, the maximum steady-state voltage ap-
pearing at the switch, when it is off, is set by the transformer
turns ratio, N, the output voltage, V
OUT, and the maximum in-
put voltage, V
IN (Max):
V
SW(OFF) = VIN (Max) + (VOUT +VF)/N
where V
F is the forward biased voltage of the output diode,
and is typically 0.5V for Schottky diodes and 0.8V for ultra-
fast recovery diodes. In certain circuits, there exists a voltage
spike, V
LL, superimposed on top of the steady-state voltage .
Usually, this voltage spike is caused by the transformer leak-
age inductance and/or the output rectifier recovery time. To
“clamp” the voltage at the switch from exceeding its maximum
value, a transient suppressor in series with a diode is inserted
across the transformer primary.
If poor circuit layout techniques are used, negative voltage
transients may appear on the Switch pin. Applying a negative
voltage (with respect to the IC's ground) to any monolithic IC
pin causes erratic and unpredictable operation of that IC. This
holds true for the LM5000 IC as well. When used in a flyback
regulator, the voltage at the Switch pin can go negative when
the switch turns on. The “ringing” voltage at the switch pin is
caused by the output diode capacitance and the transformer
leakage inductance forming a resonant circuit at the sec-
ondary(ies). The resonant circuit generates the “ringing” volt-
age, which gets reflected back through the transformer to the
switch pin. There are two common methods to avoid this
problem. One is to add an RC snubber around the output rec-
tifier(s). The values of the resistor and the capacitor must be
chosen so that the voltage at the Switch pin does not drop
below 0.4V. The resistor may range in value between 10
and 1 k
, and the capacitor will vary from 0.001 μF to
0.1 μF. Adding a snubber will (slightly) reduce the efficiency
of the overall circuit.
The other method to reduce or eliminate the “ringing” is to
insert a Schottky diode clamp between the SW pin and the
PGND pin. The reverse voltage rating of the diode must be
greater than the switch off voltage.
www.national.com
12
LM5000
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