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參數(shù)資料
| 型號： | LM4970 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | LED驅(qū)動器 |
| 英文描述： | Audio Synchronized Color LED Driver |
| 中文描述： | 音頻同步彩色LED驅(qū)動器 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 726K |
| 代理商： | LM4970 |
Application Information
(Continued)
I
2
C COMPATIBLE INTERFACE
The LM4970 uses a serial bus which conforms to the I
2
C
protocol to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector) with a pullup resis-
tor (typically 10k
). The maximum clock frequency specified
by the I
2
C standard is 400kHz. In this discussion, the master
is the controlling microcontroller and the slave is the
LM4970.
The I
2
C address for the LM4970 is determined using the
ADR pin. The LM4970’s two possible I
2
C chip addresses are
of the form 111101X
0 (binary), where X
= 0, if ADR is logic
low; and X
= 1, if ADR is logic high. If the I
2
C interface is
used to address a number of chips in a system, the
LM4970’s chip address can be changed to avoid any pos-
sible address conflicts.
The bus format for the I
2
C interface is shown in Figure 3. The
data is latched in on the rising edge of the clock. The bus
format diagram is broken up into six major sections:
The “start” signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I
2
C bus to check the incoming ad-
dress against their own address.
The 8-bit chip address is sent next, most significant bit first.
Each address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master checks
for the LM4970’s acknowledge. The master releases the
data line high (through a pullup resistor). Then the master
sends a clock pulse. If the LM4970 has received the address
correctly, then it holds the data line low during the clock
pulse. If the data line is not low, then the master should send
a “stop” signal (discussed later) and abort the transfer.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4970 received the data.
If the master has more data bytes to send to the LM4970,
then the master can repeat the previous two steps until all
data bytes have been sent.
The “stop” signal ends the transfer. To signal “stop”, the data
signal goes high while the clock signal is high. The data line
should be held high when not in use.
AUDIO SYNCHRONIZATION MODE
The LM4970 features an audio synchronization mode where
each PWM color LED driver output is dependent on the
audio input signal. The audio synchronization mode allows
each LED output to react to the amplitude of the audio input
signal, according to the LED output’s assigned frequency
band. Audio synchronization mode is activated by clearing
the I2C_SEL bit in the Pattern Select Register.
The audio synchronization filter separates the mixed audio
signal into three frequency bands: lowband, midband, and
highband. Each frequency band is assigned to a particular
PWM LED output, with lowband controlling the duty cycle of
the LED1 output, midband controlling the duty cycle of the
LED2 output, and highband controlling the duty cycle of the
LED3 output. This occurs whenever the audio synchroniza-
tion randomizer is not turned on. The operation of the audio
synchronization randomizer is explained in the
Audio Syn-
chronization Randomizer
section. The duty cycle of any
given LED output is dependent upon the amplitude of the
audio signal for its particular frequency band. An increase in
the amplitude of the audio signal will increase the duty cycle
of the PWM LED driver. LEDs driven with a higher duty cycle
results in a brighter lighting effect.
The LM4970 has three single-ended analog audio inputs
designated M
IN
, L
IN
, and R
IN
, where mono voice data is
routed to M
IN
and stereo MP3 or stereo FM radio data is
routed to L
IN
and R
IN
.Audio signals coupled in from M
IN
, L
IN
,
and R
IN
are mixed together by an audio input summing
amplifier. The gain of the audio input summing amplifier is
programmed by the SGAIN
<
2:0
>
bits of the Gain Select
Register. Increasing the gain of the audio input summing
amplifier will increase the intensity of the LEDs in audio
synchronization mode.
The pole of the low pass filter band is set by the filter cap,
Cfilt, and an internal 4k
resistor. The pole of the high pass
filter band is internally set by programming the HPF_F
<
1:0
>
bits of the Frequency Select Register. The midband fre-
quency band is a function of the lowband and highband
poles. The gain response of the midband frequency band
can be set by programming the MGAIN
<
2:0
>
bits of the
Gain Select Register.
AUDIO SYNCHRONIZATION RANDOMIZER
The LM4970 features a randomizer block that randomizes
the frequency band assigned to each PWM LED driver dur-
ing audio synchronization operation. The randomizer is acti-
vated by setting the RAND bit in the Mode Select Register.
Clearing the RAND bit will disable the randomizer. The ran-
domizer can only be activated when the LM4970 is pro-
grammed to audio synchronization mode. The interval at
which randomizer assigns a new frequency band is set to
occur once every 3.2 seconds. The randomizer ensures that
all the colored LEDs will light up over a long duration even if
the audio input has a fixed frequency.
I
2
C PATTERN MODE
The LM4970 features an I
2
C pattern mode for applications
where direct control of the LED outputs is required. I
2
C
pattern mode is activated by setting the I2C_SEL bit in the
Pattern Select Register. The LED1 output duty cycle can be
programmed to 100% by setting the I2C_LED1 bit in the
Pattern Select Register. Clearing the I2C_LED1 bit sets the
LED1 output duty cycle to 0%. The LED2 output duty cycle
can be programmed to 100% by setting the I2C_LED2 bit in
the Pattern Select Register. Clearing the I2C_LED2 bit sets
the LED2 output duty cycle to 0%. The LED3 output duty
cycle can be programmed to 100% by setting the I2C_LED3
bit in the Pattern Select Register. Clearing the I2C_LED3 bit
sets the LED3 output duty cycle to 0%. Color LEDs driven at
100% duty cycle are fully on, and driven at 0% duty cycle are
fully off.
PWM FREQUENCY
The PWM frequency of the color LED drivers is programmed
through the PWM_F
<
1:0
>
bits of the Frequency Select
Register. The LM4970 features four different PWM fre-
quency settings: 15kHz, 60Hz, 7Hz, and 4Hz. PWM fre-
quency is analogous to the sampling rate of the audio input
signal. A higher PWM frequency setting will result in a more
accurate LED representation of the audio input signal in the
audio synchronization mode. However, a PWM frequency
that is set too high will decrease the ON time of the LED
L
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12
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