參數(shù)資料
型號: LM4935WLX
廠商: National Semiconductor Corporation
元件分類: ADC
英文描述: Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC
中文描述: 音頻子系統(tǒng)的雙模單聲道立體聲耳機和揚聲器放大器的高效率和多功能模數(shù)轉(zhuǎn)換器
文件頁數(shù): 15/112頁
文件大?。?/td> 5017K
代理商: LM4935WLX
10.0 Electrical Characteristics
(Notes 1, 2) Unless otherwise stated
PLL_V
DD
= 3.3V, D_V
DD
= 3.3V,
BB_V
DD
= 1.8V, A_V
= 3.3V, LS_V
= 3.3V.
The following specifications apply for the circuit shown in
Figure 2
unless
otherwise stated. Limits apply for 25C. (Continued)
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits.
Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device
is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device
performance.
Note 2:
All voltages are measured with respect to the relevant V
SS
pin unless otherwise specified.All grounds should be coupled as close as possible to the device.
Note 3:
The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJ
,
θ
, and the ambient temperature, T
A
. The maximum
allowable power dissipation is P
DMAX
= (T
JMAX
– T
A
)/
θ
JA
or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4:
Human body model: 100pF discharged through a 1.5k
resistor.
Note 5:
Machine model: 220pF – 240pF discharged through all pins.
Note 6:
Typical values are measured at 25C and represent the parametric norm.
Note 7:
Limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level).
Note 8:
Best operation is achieved by maintaining 3.0V
<
A_V
DD
<
5.0 and 3.0V
<
D_V
DD
<
3.6V and A_V
DD
>
D_V
DD
.
Note 9:
Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled.
Note 10:
Disabling or bypassing the PLL will usually result in an improvement in noise measurements.
L
www.national.com
15
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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