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參數(shù)資料
| 型號： | LM4817MH/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 1.5 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO28 |
| 封裝： | 4.40 MM, TSSOP-28 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 1119K |
| 代理商： | LM4817MH/NOPB |
Application Information (Continued)
Power Dissipation
Power dissipation refers to the part’s ability to radiate heat
away from the silicon, with packaging being a key factor. A
reasonable analogy is the packaging a human being might
wear, a jacket for example. A jacket keeps a person comfort-
able on a cold day, but not so comfortable on a hot day. It
would be even worse if the person was exerting power
(exercising). This is because the jacket has resistance to
heat flow to the outside ambient air, like the IC package has
a thermal resistance from its junctions to the ambient (
θ
JA).
θ
JA has a unit of temperature per power and can be used to
calculate the IC’s junction temperature as follows:
T
J =
θ
JA (PD) + TA
T
J is the junction temperature of the IC.
θ
JA is the thermal
resistance from the junction to the ambient air outside the
package. PD is the power exerted by the IC, and T
A is the
ambient temperature.
PD is calculated as follows:
PD=I
OUT (VIN -VO)
θ
JA for the LM4817 package (MSOP-8) is 223C/W with no
forced air flow, 182C/W with 225 linear feet per minute
(LFPM) of air flow, 163C/W with 500 LFPM of air flow, and
149C/W with 900 LFPM of air flow.
θ
JA can also be decreased (improved) by considering the
layout of the PC board: heavy traces (particularly at V
IN and
the two V
OUT pins), large planes, through-holes, etc.
Improvements and absolute measurements of the
θ
JA can
be estimated by utilizing the thermal shutdown circuitry that
is internal to the IC. The thermal shutdown turns off the pass
transistor of the device when its junction temperature
reaches 160C (Typical). The pass transistor doesn’t turn on
again until the junction temperature drops about 10C (hys-
teresis).
Using the thermal shutdown circuit to estimate ,
θ
JA can be
done as follows: With a low input to output voltage differen-
tial, set the load current to 300mA. Increase the input voltage
until the thermal shutdown begins to cycle on and off. Then
slowly decrease V
IN (100mV increments) until the part stays
on. Record the resulting voltage differential (V
D) and use it in
the following equation:
Fault Detection
The LDO provides a FAULT pin that goes low during out of
regulation conditions like current limit and thermal shutdown,
or when it approaches dropout. The latter monitors the input-
to-output voltage differential and compares it against a
threshold that is slightly above the dropout voltage. This
threshold also tracks the dropout voltage as it varies with
load current. Refer to Fault Detect vs. Load Current curve in
the typical characteristics section.
The FAULT pin requires a pull-up resistor since it is an
open-drain output. This resistor should be large in value to
reduce energy drain. A 100k
pull-up resistor works well for
most applications.
Figure 6 shows the LDO’s with delay added to the FAULT pin
for the reset pin of a microprocessor. The output of the
comparator stays low for a preset amount of time after the
regulator comes out of a fault condition.
The delay time for the application of Figure 5 is set as
follows:
The application is set for a reset delay time of 8.8ms. Note
that the comparator should have high impedance inputs so
as to not load down the V
REF at the CC pin of the LM4817.
Shutdown
The LM4817’s LDO goes into sleep mode when the SHDN
pin is in a logic low condition. During this condition, the pass
transistor, error amplifier, and bandgap are turned off, reduc-
ing the supply current to 1nA typical. The maximum guaran-
teed voltage for a logic low at the SHDN pin is 0.4V. A
minimum guaranteed voltage of 2V at the SHDN pin will turn
the LDO back on. The SHDN pin may be directly tied to V
IN
to keep the part on. The SHDN pin may exceed V
IN but not
the ABS MAX of 6.5V.
Figure 6 shows an application that uses the SHDN pin. It
detects when the battery is too low and disconnects the load
by turning off the regulator. A micropower comparator
(LMC7215) and reference (LM385) are combined with resis-
tors to set the minimum battery voltage. At the minimum
battery voltage, the comparator output goes low and tuns off
the LDO and corresponding load. Hysteresis is added to the
minimum battery threshold to prevent the battery’s recovery
voltage from falsely indicating an above minimum condition.
When the load is disconnected from the battery, it automati-
cally increases in terminal voltage because of the reduced IR
drop across its internal resistance. The Minimum battery
detector of figure 6 has a low detection threshold (V
LT)of
3.6V that corresponds to the minimum battery voltage. The
upper threshold (V
UT) is set for 4.6V in order to exceed the
recovery voltage of the battery.
200781B9
FIGURE 6. Power on Delayed Reset Application
LM4817
www.national.com
18
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