Operation
(Continued)
Now R
can be chosen with the selected value for C
C
.
Check to make sure that the pole f
is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure
both component values are in the recommended range.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or
just to improve the overall phase margin of the control loop,
another pole may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
tor, C
C2
, directly from the compensation pin V
C
to ground, in
parallel with the series combination of R
C
and C
C
. The pole
should be placed at the same frequency as f
Z1
, the ESR
zero. The equation for this pole follows:
To ensure this equation is valid, and that C
C2
can be used
without negatively impacting the effects of R
C
and C
C
, f
PC2
must be greater than 10f
ZC
.
CHECKING THE DESIGN
With all the poles and zeros calculated the crossover fre-
quency can be checked as described in the section
DC Gain
and Open-loop Gain
. The compensation values can be
changed a little more to optimize performance if desired.
This is best done in the lab on a bench, checking the load
step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of R
C
should be chosen. This will improve the overall bandwidth
which makes the regulator respond more quickly to tran-
sients. If more detail is required, or the most optimum per-
formance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
POWER DISSIPATION
The output power of the LM3310 is limited by its maximum
power dissipation. The maximum power dissipation is deter-
mined by the formula
P
D
= (T
jmax
- T
A
)/
θ
JA
where T
jmax
is the maximum specified junction temperature
(125C), T
A
is the ambient temperature, and
θ
JA
is the ther-
mal resistance of the package.
LAYOUT CONSIDERATIONS
The input bypass capacitor C
, as shown in the typical
operating circuit, must be placed close to the IC. This will
reduce copper trace resistance which effects input voltage
ripple of the IC. For additional input voltage filtering, a 100nF
bypass capacitor can be placed in parallel with C
, close to
the V
pin, to shunt any high frequency noise to ground. The
output capacitor, C
, should also be placed close to the
IC. Any copper trace connections for the C
capacitor can
increase the series resistance, which directly effects output
voltage ripple. The feedback network, resistors R
and
R
, should be kept close to the FB pin, and away from the
inductor, to minimize copper trace connections that can in-
ject noise into the system. R
and C
should also be close to
the RE and CE pins to minimize noise in the GPM circuitry.
Trace connections made to the inductor and schottky diode
should be minimized to reduce power dissipation and in-
crease overall efficiency. For more detail on switching power
supply layout considerations see Application Note AN-1149:
Layout Guidelines for Switching Power Supplies
.
For Op-Amp layout please refer to the
Operational Amplifier
section.
Figure 6
,
Figure 7
, and
Figure 8
in the Application Informa-
tion section following show the schematic and an example of
a good layout as used in the LM3310/11 evaluation board.
L
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