Application Information
(Continued)
The LM3208 converts higher input voltage to lower output
voltage with high efficiency. This is achieved with an
inductor-based switching topology. During the first half of the
switching cycle, the internal PMOS switch turns on, the input
voltage is applied to the inductor, and the current flows from
PV
IN
line into the output capacitor and the load through the
inductor. During the second half cycle, the PMOS turns off
and the internal NMOS turns on. The inductor current con-
tinues to flow via the inductor from the device PGND line into
the output capacitor and the load.
Referring to
Figure 4
, a pulse current flows in the left hand
side loop, and a ripple current flows in the right hand side
loop. Board layout and circuit pattern design of these two
loops are the key factors for reducing noise radiation and
stable operation. In other lines, such as from battery to C1
and C2 to the load, the current is mostly DC current. There-
fore, it is not necessary to take so much care. Only pattern
width (current capability) and DCR drop considerations are
needed.
BOARD LAYOUT FLOW
1.
Minimize C1, PV
, and PGND loop. These traces
should be as wide and short as possible. This is the
highest priority.
2.
Minimize L1, C2, SW and PGND loop. These traces also
should be wide and short. This is the second priority.
3.
The above layout patterns should be placed on the
component side of the PCB to minimize parasitic induc-
tance and resistance due to via-holes. It may be a good
idea that the SW to L1 path is routed between C1(+) and
C1(-) land patterns. If vias are used in these large cur-
rent paths, multiple via-holes should be used if possible.
4.
Connect C1(-), C2(-) and PGND with wide GND pattern.
This pattern should be short, so C1(-), C2(-), and PGND
should be as close as possible. Then connect to a PCB
common GND pattern with as many via-holes as pos-
sible.
5.
SGND should not connect directly to PGND. Connecting
these pins under the device should be avoided. (If pos-
sible, connect SGND to the common port of C1(-), C2(-)
and PGND.)
6.
V
should not be connected directly to PV
. Connect-
ing these pins under the device should be avoided. It is
good idea to connect V
DD
to C1(+) to avoid switching
noise injection to the V
DD
line.
7.
The FB line should be protected from noise. It is a good
idea to use an inner GND layer (if available) as a shield.
Note:
The evaluation board shown in
Figure 5
for the LM3208 was designed
with these considerations, and it shows good performance. However
some aspects have not been optimized because of limitations due to
evaluation-specific requirements. The board can be used as a refer-
ence. Please refer questions to a National representative.
20166309
FIGURE 5. Evaluation Board Layout
L
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