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| 型號： | LM2642 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 504K |
| 代理商： | LM2642 |
Application Information
(Continued)
Looking at the plot, it can be seen that the unity-gain cross-
over frequency f
is expected to be about 25 kHz. Using this
value, the phase margin at the point is calculated to be about
84.
To verify the accuracy of these calculations, the circuit was
bench tested using a network analyzer. The measured gain
and phase are shown plotted in Figure 7
The measured gain plot agrees very closely to the predicted
values. The phase margin at 0 dB is slightly less than
predicted (71 vs. 84), which is to be expected due to the
negative phase shift contributions of high frequency poles
not included in this simplified analysis.
It should be noted that 70 phase margin with 25 kHz band-
width is excellent, and represents the optimal compensation
for this set of values for V
IN
, V
OUT
, inductor and R
L
.
Optimizing Stability
The best tool for measuring both bandwidth and phase
margin is a network analyzer. If this is not available, a simple
method which gives a good measure of loop stability is to
apply a minimum to maximum step of output load current
and observe the resulting output voltage transient. A design
which has good phase margin (
>
50) will typically show no
ringing after the output voltage transient returns to its nomi-
nal value.
It should be noted that the stability (phase margin) does not
have to be optimal for the regulator to be stable. The design
analyzed in the previous section was re-compensated by
changing R11 and C10 to intentionally reduce the phase
margin to about 35 and re-tested for step response. The
output waveform displayed slight ringing after the initial re-
turn to nominal, but was completely stable otherwise.
In most cases, the compensation components shown in the
Typical Application Circuits will give good performance. To
assist in optimizing phase margin, the following guidelines
show the effects of changing various components.
C
:
Increasing the capacitance of C
moves the fre-
quency of the pole f
(C
) to a lower value and reduces
loop bandwidth. Increasing C
can be beneficial (increas-
ing the phase margin) if the loop bandwidth is too wide
(
>
F
/5) which places the high-frequency poles too close
to the unity-gain crossover frequency.
ESR of C
:
The ESR forms a zero f
z
(ESR), which is
needed to cancel negative phase shift near the unity-gain
frequency. High-ESR capacitors can not be used, since the
zero will be too low in frequency which will make the loop
bandwidth too wide.
R11/C10:
These form a pole and a zero. Changing the value
of C10 changes the frequency of both the pole and zero.
Note that since this causes the frequency of both the pole
and zero to move up or down together, adjusting the value of
C10 does not significantly affect loop bandwidth.
Changing the value of R11 moves the frequency location of
the zero f
(R11), but does not significantly shift the C10 pole
(since the value of R11 is much less than the 160 k
output
impedance of the Gm amplifier). Since only the zero is
moved, this affects both bandwidth and phase margin. This
means adjusting R11 is an easy way to maximize the posi-
tive phase shift provided by the zero. Best results are typi-
cally obtained if f
(R11) is in the frequency range of f
c
/4 to f
c
(where f
c
is the unity-gain crossover frequency).
Design Procedure
This section presents guidelines for selecting external com-
ponents.
INDUCTOR SELECTION
In selecting an inductor, the parameters which are most
important are inductance, current rating, and DC resistance.
Inductance
It is important to understand that all inductors are not created
equal, as the method of specifying inductance varies widely.
It must also be noted that the inductance of every inductor
decreases with current. The core material, size, and con-
struction type all contribute the the inductor’s dependence
on current loading. Some inductors exhibit inductance
curves which are relatively flat, while others may vary more
than 2:1 from minimum to maximum current. In the latter
10014807
FIGURE 6. Calculated Gain Plot for 3.3V/4A Application
10014808
FIGURE 7. Measured Gain/Phase Plot for 3.3V/4A
Application
L
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