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參數(shù)資料
| 型號： | LM2640MTC-ADJ |
| 英文描述： | Current-Mode SMPS Controller |
| 中文描述： | 電流模式開關(guān)電源控制器 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 504K |
| 代理商： | LM2640MTC-ADJ |
Application Information
(Continued)
5V LIN Output
The LM2640 contains a built-in 5V/50 mA LDO regulator
whose output is connected to the LIN pin. Since this is an
LDO regulator, it does require an external capacitor to main-
tain stability. The minimum amount of capacitance required
for stability is 4.7 μF, with ESR in the range of about 100 m
to 3
. A good quality solid Tantalum capacitor is recom-
mended (ceramics can not be used because the ESR is too
low). If cold temperature operation is required, a capacitor
must be selected which has an ESR that is in the stable
range over the entire operating temperature range of the
application.
Since the current limit for this LDO regulator is set at about
85 mA, it can be used at load currents up to about 50 mA
(assuming total IC power dissipation does not exceed the
maximum value).
Guaranteed specifications are provided for worst-case val-
ues of V
LIN
over the full operating temperature range for load
currents up to 25 mA (see Electrical Characteristics). To
estimate how the V
LIN
output voltage changes when going
from I
LIN
= 25 mA to I
LIN
= 50 mA, a change in V
LIN
of about
30 mV should be expected due to loading (typical value
only, not guaranteed). This decrease in V
LIN
is linear with
increasing load current.
It must be understood that the maximum allowable current of
50mA must include the current drawn by the gate drive
circuitry. This means that the maximum current available for
use at the LIN pin is 50 mA minus whatever is being used
internally for gate drive.
The amount of current used for gate drive by each switching
output can be calculated using the formula:
I
GD
= 2 X Q X F
OSC
Where:
I
GD
is the gate drive current supplied by V
LIN
.
Q is the gate charge required by the selected FET (see FET
data sheet: Gate Charge Characteristics).
F
OSC
is the switching frequency.
Example: As shown in the typical application, if the FET
NDS8410 is used with the LM2640, the turn-on gate voltage
(V
) is 5V V
= 4.3V. Referring to the NDS8410 data
sheet, the curve Gate Charge Characteristics shows that the
gate charge for this value of V
GS
is about 24 nC.
Assuming 200 kHz switching frequency, the gate drive cur-
rent used by each switching output is:
I
GD
= 2 X Q X F
OSC
= 2 X (24 X 10
9
) X (2 X 10
5
)
= 9.6 mA
If both outputs are switching, the total gate drive current
drawn would be twice this (19.2 mA).
Note that in cases where the voltage at switching output
#
1
is 4.8V or higher, the internal gate drive current is obtained
from that output (which means the full 50 mA is available for
external use at the LIN pin).
SYNC Pin
The basic operating frequency of 200 kHz can be increased
to up to 400 kHz by using the SYNC pin and an external
CMOS or TTL clock. The synchronizing pulses must have a
minimum pulse width of 200 ns.
If the sync function is not used, the SYNC pin must be
connected to the LIN pin or to ground to prevent false
triggering.
Current Limit Circuitry
The LM2640 is protected from damage due to excessive
output current by an internal current limit comparator, which
monitors output current on a cycle-by-cycle basis. The cur-
rent limiter activates when ever the absolute magnitude of
the voltage developed across the output sense resistor ex-
ceeds 100 mV (positive or negative value).
If the sensed voltage exceeds 100 mV, the high-side FET
switch is turned OFF. If the sensed voltage goes below -100
mV, the low-side FET switch is turned OFF. It should be
noted that drawing sufficient output current to activate the
current limit circuits can cause the output voltage to drop,
which could result in a under-voltage latch-OFF condition
(see next section).
Under-voltage/Over-voltage Protection
The LM2640 contains protection circuitry which activates if
the output voltage is too low (UV) or too high (OV). In the
event of either a UV or OV fault, the LM2640 is latched off
and the high-side FET is turned off, while the low-side FET is
turned on.
If the output voltage drops below 70% of nominal value, the
under-voltage comparator will latch OFF the LM2640. To
restore operation, power to the device must be shut off and
then restored.
It should be noted that the UV latch provides protection in
cases where excessive output current forces the output
voltage down. The UV latch circuitry is disabled during
start-up.
If the output voltage exceeds 150% of nominal, the
over-voltage comparator latches off the LM2640. As stated
before, power must be cycled OFF and then ON to restore
operation.
It must be noted that the OV latch can not protect the load
from damage in the event of a high-side FET switch failure
(where the FET shorts out and connects the input voltage to
the load).
Protection for the load in the event of such a failure can be
implemented using a fuse in the power lead. Since the
low-side FET switch turns ON whenever the OV latch acti-
vates, this would blow a series fuse if the FET and fuse are
correctly sized.
Soft-Start
An internal 5 μA current source connected to the soft-start
pins allows the user to program the turn-on time of the
LM2640. If a capacitor is connected to the SS pin, the
voltage at that pin will ramp up linearly at turn ON. This
voltage is used to control the pulse widths of the FET
switches.
The pulse widths start at a very narrow value and linearly
increase up to the point where the SS pin voltage is about
1.3V. At that time, the pulse-to-pulse current limiter controls
the pulse widths until the output reaches its nominal value
(and the PWM current-mode control loop takes over).
The LM2640 contains a digital counter (referenced to the
oscillator frequency) that times the soft-start interval. The
maximum allotted SS time period is 4096 counts of the
oscillator clock, which means the time period varies with
oscillator frequency:
max. allowable SS interval = 4096 / F
OSC
L
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