MOSFET Selection
(Continued)
Therefore the total gate charge of both FETs should be
limited to less than 20nC at 4.5V V
GS
. The lower the number
the faster the FETs should switch and the better the effi-
ciency.
RISE / FALL TIMES
A better indication of the actual switching times of the FETs
can be found in their electrical characteristics table. The rise
and fall time should be specified and selected to be at a
minimum. This helps improve efficiency and ensuring that
shoot through does not occur.
GATE CHARGE RATIO
Another consideration in selecting the FETs is to pay atten-
tion to the Qgd / Qgs ratio. The reason for this is that proper
selection can prevent spurious turn on. If we look at the
NFET for example, when the FET is turning off, the gate
signal will pull to ground. Conversely the PFET will be turn-
ing on, causing the SW node to rise towards V
. The gate to
drain capacitance of the NFET couples the SW node to the
gate and will cause it to rise. If this voltage is excessive, then
it could weakly turn on the low side FET causing an effi-
ciency loss. However, this coupling is mitigated by having a
large gate to source capacitance of the FET, which helps to
hold the gate voltage down. Ideally, a very low Qgd / Qgs
would be ideal, but in practice it is common to find the
number around 1. As a general rule, the lower the ratio, the
better.
If the above selection criteria have been met it is useful to
generate a figure of merit to allow comparison between the
FETs. One such method is to multiply the R
of the FET
by the total gate charge. This allows an easy comparison of
the different FETs available. Once again, the lower the prod-
uct, the better.
FEEDBACK RESISTORS
The feedback resistors are used to scale the output voltage
to the internal reference value such that the loop can be
regulated. The feedback resistors should not be made arbi-
trarily large as this creates a high impedance node at the
feedback pin that is more susceptible to noise. A combined
value of 50k
for the two resistors is adequate. To calculate
the resistor values use the equation below. Typically the low
side resistor is initially set to a pre-determined value such as
10 k
.
V
FB
is the internal reference voltage that can be found in the
electrical characteristics table or approximated by 0.8V.
The output voltage value can be set in a precise manner by
taking into account the fact that the reference voltage is
regulating the bottom of the output ripple as opposed to the
average value. This relationship is shown in the figure below.
20166223
It can be seen that the average output voltage (VOUT_AC-
TUAL) is higher than the output voltage (VOUT_SET) that
was calculated by the earlier equation by exactly half the
output voltage ripple. The output voltage that is targeted for
regulation may then be appended according to the voltage
ripple. This can be seen below:
V
OUT_ACTUAL
= V
OUT_SET
+
1
2
V
OUT
= V
OUT_SET
+
1
2
I
L
x
R
ESR
Efficiency Calculations
One of the most important parameters to calculate during the
design stage is the expected efficiency of the system. This
can help determine optimal FET selection and can be used
to calculate expected temperature rise of the individual com-
ponents. The individual losses of each component are bro-
ken down and the equations are listed below:
QUIESCENT CURRENT
The quiescent current consumed by the LM1770 is one of
the major sources of loss within the controller. However, from
a system standpoint this is usually less than 0.5% of the
overall efficiency. Therefore, it could easily be omitted but is
shown for completeness:
P
IQ
= V
IN
x I
Q
CONDUCTION LOSS
There are three losses associated with the external FETs.
From the DC standpoint there is the I-squared R loss,
caused by the on resistance of the FET. This can be mod-
eled for the PMOS by:
P
P_COND
= D x R
DSON_PMOS
x I
OUT2
and the NMOS by:
P
N_COND
= (1 - D) x R
DSON_NMOS
x I
OUT2
L
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