參數(shù)資料
型號(hào)： LM1262NA
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 音頻／視頻放大
英文描述： 200 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs
中文描述： 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24
封裝： PLASTIC, DIP-24
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 1122K
代理商： LM1262NA
DAC Interface Register Definitions
(Continued)
DAC 3 Register (I
2
C address 06h)
Register name: DAC 3 (06h)
Bit 7
D3–7
Bits 7–0: DAC 3. These eight bits determine the output
voltage of DAC 3.
Bit 0
D3–0
D3–6
D3–5
D3–4
D3–3
D3–2
D3–1
DAC 4 Register (I
2
C address 07h)
Register name: DAC 4 (07h)
Bit 7
D4–7
Bits 7–0: DAC 4. These eight bits determine the output
voltage of DAC 4.
Bit 0
D4–0
D4–6
D4–5
D4–4
D4–3
D4–2
D4–1
DC Offset and OSD Contrast Control Register (I
2
C ad-
dress 08h)
Register name: DC Offset/OSD Cont. (08h)
Bit 7
RSV
Bits 2–0: DC Offset Control. These three bits determine the
active video DC offset to all three channels.
Bits 4–3: OSD Contrast Control. These two bits determine
the contrast level of the digital OSD information.
Bits 7–5: Reserved.
Bit 0
DC0
RSV
RSV
OSDC1
OSDC0
DC2
DC1
Global Video Control Register (I
2
C address 09h)
Register name: Global Control (09h)
Bit 7
RSV
Bit 0:
Bit 0
BV
RSV
Blank Video. When this bit is a one, blank the
video output. When this bit is a zero allow normal
video out.
Power Save. When this bit is a one, shut down
the analog circuits to support sleep mode. When
this bit is a zero enable the analog circuits for
normal operation.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
DAC1–3 Configuration. When this bit is a zero
the DAC outputs of DAC1–3 are full scale
(0V–4.5V). When this bit is 1, the range of
DAC1–3 are halved (0V–2.25V).
DAC4 Configuration. When this bit is a zero the
DAC4 output is not mixed with the other DAC
outputs. When the bit is one, 50% of the DAC4
output is added to DAC1–3.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
Bits 7–6: Reserved.
0
DCF4
DCF1–3
0
PS
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Increment Mode Register (I
2
C address 0Ah)
Register name: Increment Mode (0Ah)
Bit 7
RSV
Bit 0:
Bit 0
INCR
RSV
Increment Enable. When set to a “0”, the default
value, the increment mode is enabled. This al-
lows the registers to be updated sequentially by
sending another block of data.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
Bits 7–2: Reserved.
RSV
RSV
RSV
RSV
0
Bit 1:
Clamp Polarity, Vertical Blanking, and OSD Control (I
2
C
address 0Bh)
Register name: Clamp/VBL/OOR (0Bh)
Bit 7
RSV
Bit 0:
Bit 0
OOR
RSV
RSV
RSV
CLMP
DAC4
VBL
OSD Only Register: When this bit is 0 (default)
normal video operation is assumed. When this bit
is 1, the video is blanked, only the OSD window is
displayed (used for “out-of-range” condition).
Vertical Blank Enable: When this bit is set to 1 the
vertical blanking pulse is OR’d with the horizontal
blank pulse at the preamplifier output, to blank
the video during both the vertical and horizontal
retrace. I
2
C changes for contrast and DAC4 will
only be updated during vertical retrace period.
When this bit is set to 0 (default) the internal
vertical blanking is disabled (horizontal blanking
is not affected) and I
2
C changes for contrast and
DAC4 occur anytime in the video field. NOTE: If
there is no vertical signal to the LM1262, this bit
must be set to a 0 for proper operation.
DAC4 I/O Switch: When this bit is set to 1 (de-
fault) DAC4 output is enabled. When this bit is set
to a 0 the DAC4 output is disabled and pin 13 is
used for the vertical blank input. DAC4 can still be
connected internally to DAC1-3. When both bits 1
and 2 are set to 1 vertical blanking will be stripped
from the sandcastle pulse at pin 23. For proper
detection of the sandcastle pulse the CLMP bit
(bit 3) must be set to a 0, positive polarity for the
clamp input.
Determines the polarity of the clamp signal used
by the LM1262, “0” (default) is a positive clamp
signal, “1” is a negative going clamp signal.
Bits 7–4: Reserved.
Bit 1:
Bit 2:
Bit 3:
Software Reset Register (I
2
C address 0Fh)
Register name: Software Reset (0Fh)
Bit 7
RSV
Bit 0:
Bit 0
SRST
RSV
RSV
RSV
RSV
RSV
RSV
Software Reset. Setting this bit causes a software
reset. All registers (except this one) are loaded
with their default values. All operations currently
in progress are aborted (except for I
2
C transac-
tions). This bit automatically clears itself when the
reset has been completed.
Bits 7–1: Reserved.
L
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