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參數(shù)資料
| 型號： | LM1262 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 視頻放大器 |
| 英文描述： | 200 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs |
| 中文描述： | 200 MHz的I2C兼容的RGB視頻放大器系統(tǒng)的OSD和DAC的 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 1122K |
| 代理商： | LM1262 |
External Interface Signals Electrical Characteristics
(Continued)
Unless otherwise noted: T
A
= 25C, V
CC
= +5V, V
IN
= 0.7V, V
ABL
= V
CC
, C
L
= 5 pF, Video Output = 2V
P-P
.
Symbol
Parameter
Conditions
Min
(Note 7)
Typ
(Note 6)
Max
(Note 7)
Units
t
H-Blank on
H-Blank Time Delay from Zero
Crossing Point of H Flyback
H-Blank Time Delay from Zero
Crossing Point of H Flyback
I
In
H-Blank Detection
Threshold
Minimum—Insure Normal
Operation
Maximum—Should Not
Exceed in Normal Operation
Peak Current during Flyback
Period, Recommended Design
Range
Rising Edge of the Flyback
Signal
Falling Edge of the Flyback
Signal
50
ns
t
H-Blank off
50
ns
I
In Threshold
20
μA
I
In-Operating
Lowest Operating Horizontal
Frequency in Given Application
(Note 17)
30
300
μA
I
In Flyback
Operating Range for all
Horizontal Scan Frequencies,
Maximum Current Should Not
Exceed 2 mA (Note 17)
0.5
1.5
2.0
mA
Note 1:
Limits of Absolute Maximum Ratings indicate limits below which damage to the device must not occur.
Note 2:
Limits of operating ratings indicate required boundaries of conditions for which the device is functional, but may not meet specific performance limits.
Note 3:
All voltages are measured with respect to GND, unless otherwise specified.
Note 4:
Human body model, 100 pF discharged through a 1.5 k
resistor.
Note 5:
Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50
).
Note 6:
Typical specifications are specified at +25C and represent the most likely parametric norm.
Note 7:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8:
The supply current specified is the quiescent current for V
CC
with R
L
=
∞
. Load resistors are not required and are not used in the test circuit, therefore all
the supply current is used by the pre-amp.
Note 9:
Linearity Error is the variation in step height of a 16 step staircase input signal waveform with 0.7 V
P-P
level at the input, subdivided into 16 equal steps,
with each step approximately 100 ns in width.
Note 10:
Input from signal generator: t
r
, t
f
<
1 ns. Scope and generator response used for testing: t
r
= 1.1 ns, t
f
= 0.9 ns. Using the RSS technique the scope and
generator response have been removed from the output rise and fall times.
Note 11:
A
V
track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in
gain change between any two amplifiers with the contrast set to A
V 1/2
and measured relative to the A
V
max condition. For example, at A
V
max the three amplifiers’
gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to A
V 1/2
. This yields a typical gain change of
10.0 dB with a tracking change of
±
0.2 dB.
Note 12:
ABL should provide smooth decrease in gain over the operational range of 0 dB to –6 dB
A
ABL
= A(V
ABL
= V
ABL Max Gain
) - A(V
ABL
= V
ABL Min Gain
)
Beyond –6 dB the gain characteristics, linearity, pulse response, and/or behavior may depart from normal values.
Note 13:
Adjust input frequency from 10 MHz (A
V
max reference level) to the 3 dB corner frequency (f
3 dB
).
Note 14:
Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier
inputs to simulate generator loading. Repeat test at f
IN
= 10 MHz for V
sep 10 MHz
.
Note 15:
A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer
clamp pulse may be required.
Note 16:
The internal circuit detects the vertical blank only when this signal is present in the sandcastle input. There is typically an 800 nsec delay in detecting the
vertical blank signal. If only the horizontal clamp is present the vertical blank will not be activated. Rise and fall times of the sandcastle input signal should be 10 nsec
or faster.
Note 17:
Limits met by matching the external resistor going to pin 24 to the H Flyback voltage.
Note 18:
A 4.7 k
resistor must be in series with pin 13 when this pin is the input for vertical blanking. When the LM1262 is first turned on the default condition for
pin 13 is for the DAC4 output. Under this condition pin 13 will be damaged by the vertical blanking input if a series resistor is not used.
L
www.national.com
5
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| LM1262NA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:200 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs |
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| LM1267NA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs |
| LM1267NA/NOPB | 功能描述:IC PREAMP RGB 150MHZ 24-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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