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參數(shù)資料
| 型號： | LM1253 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| 中文描述： | 單片三180兆赫的I2C顯像管預(yù)先集成在屏幕顯示（OSD）發(fā)生器模擬放大器 |
| 文件頁數(shù)： | 27/57頁 |
| 文件大?。?/td> | 1621K |
| 代理商： | LM1253 |
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Micro-Controller Interface
The micro-controller interfaces to the LM1253A pre-amp via
an I
2
C interface. The protocol of the interface begins with a
Start Pulse followed by a byte comprised of a seven bit Slave
Device Address and a Read/Write bit. Since the first byte is
composed of both the address and the read/write bit the ad-
dress of the LM1253A for writing is BAh (1011 1010) and the
address for reading is BBh (1011 1011). The development
software provided by National Semiconductor will automati-
cally take care of the difference between the read and write
addresses if the target address under the communications
tab is set to BAh. Figures 39, 40 show a write and read se-
quence across the I
2
C interface.
Write Sequence
The write sequence begins with a start condition which con-
sists of the master pulling SDA low while SCL is held high.
The slave device address is next sent. The address byte is
made up of an address of seven bits (7-1) and the read/write
bit (0). Bit 0 is low to indicate a write operation. Each byte
that is sent is followed by an acknowledge. When SCL is
high the master will release the SDAline. The slave must pull
SDAlow to acknowledge. The register to be written to is next
sent in two bytes, the least significant byte being sent first.
The master can then send the data, which consists of one or
more bytes. Each data byte is followed by an acknowledge
bit. If more than one data byte is sent the data will increment
to the next address location. See Figure 39
Read Sequence
Read sequences are comprised of two I
2
C transfer se-
quences: The first is a write sequence that only transfers the
two byte address to be accessed. The second is a read se-
quence that starts at the address transferred in the previous
address only write access and increments to the next ad-
dress upon every data byte read. This is shown in Figure 40
DS101265-45
FIGURE 39. I
2
C Write Sequence
L
www.national.com
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LM1253AN | Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| LM1253A | Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| LM1262 | 200 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs |
| LM1262NA | 200 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs |
| LM1267NA | 150 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM1253A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| LM1253AN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| LM-1256 | 制造商:ROHM 制造商全稱:Rohm 功能描述:16 x 16 matrix displays |
| LM-1256_1 | 制造商:ROHM 制造商全稱:Rohm 功能描述:16】16 matrix displays |
| LM-1256LB1 | 制造商:ROHM 制造商全稱:Rohm 功能描述:16】16 matrix displays |
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