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參數(shù)資料
| 型號： | LK1301-9RD0B1 |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT 150 W AC-DC REG PWR SUPPLY MODULE |
| 封裝： | METAL, CASE K02, MODULE |
| 文件頁數(shù)： | 14/27頁 |
| 文件大小： | 640K |
| 代理商： | LK1301-9RD0B1 |
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K-Family
DC-DC Converters >100 W
Rugged Environment
8 - 22
Edition 2/96 - Melcher AG
MELCHER
The Power Partners.
8.1
Fig. 24
Option D1...D0: JFET output, ID ≤ 2.5 mA
NPN output (D5...DD):
Connector pin D is internally connected via the collector-
emitter path of a NPN transistor to the negative potential of
output 1.
UD < 0.4 V (logic low) corresponds to a monitored
voltage level (
Ui and/or Uo1) > Ut +Uh. The current ID
through the open collector should not exceed 20 mA. The
NPN output is not protected against external overvoltages.
UD should not exceed 40 V.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
high, H,
I D ≤ 25 A at UD = 40 V
Ui and Uo1 > Ut + Uh
low, L,
UD
≤ 0.4 V at ID = 20 mA
Threshold tolerances and hysteresis:
If
Ui is monitored, the internal input voltage after the input
filter and rectifier (LK types) is measured. Consequently
this voltage differs from the voltage at the connector pins by
the voltage drop
U
ti across input filter and rectifier. The
threshold levels of the D0 and D9 options are factory ad-
justed at nominal output current
Io nom and at TA = 25 °C. The
value of
U
ti depends upon the input voltage range (CK,
DK, ..), threshold level
Ut, temperature and input current.
The input current is a function of the input voltage and the
output power.
Fig. 26
Definition of Uti, Ut i and Uhi (JFET output)
Table 16: D-output logic signals
Version of D
Ui < Ut resp. Uo < Ut
Ui > Ut + Uh resp. Uo > Ut
Configuration
D1, D2, D3, D4, D0
low
high
JFET
D5, D6, D7, D8, D9, DD
high
low
NPN
JFET output (D0…D4):
Connector pin D is internally connected via the drain-
source path of a JFET (self-conducting type) to the nega-
tive potential of output 1.
UD ≤ 0.4 V (logic low) corresponds
to a monitored voltage level (
Ui and/or Uo1) < Ut. The cur-
rent
ID through the JFET should not exceed 2.5 mA. The
JFET is protected by a 0.5 W Zener diode of 8.2 V against
external overvoltages.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
low, L,
UD ≤ 0.4 V at ID = 2.5 mA
Ui and Uo1 > Ut + Uh
high, H,
ID
≤ 25 A at UD = 5.25 V
Vo1+
Vo1–
D
UD
ID
Vi+
Vi–
Rp
U
ti
U
hi
U
D low
U
D
U
D high
U
i
P
o
=
P
o
nom
P
o
=
0
P
o
=
0
U
ti
P
o
=
P
o
nom
Vo1+
Vo1–
D
UD ≤ 6 V
ID
Vi+
Vi–
Rp
Fig. 25
Option D5...DD: NPN output, Uo1 ≤ 40 V, ID ≤ 20 mA
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