參數(shù)資料
型號: LH543601P-30
廠商: Sharp Corporation
英文描述: 256 x 36 x 2 Bidirectional FIFO
中文描述: 256 × 36 × 2雙向先進(jìn)先出
文件頁數(shù): 13/43頁
文件大小: 360K
代理商: LH543601P-30
Table 3. Resource-Register Programming
RESOURCE-
REGISTER
ADDRESS
RESOURCE-REGISTER CONTENTS
A
2A
A
1A
A
0A
NORMAL FIFO OPERATION
D
35A
D
0A
H
H
H
X...
...X
MAILBOX
D
35A
D
0A
H
H
L
X...
...X
AF
2
, AE
2
, AF
1
, AE
1
FLAG OFFSETS REGISTER (36-BIT MODE)
D
35A
D
34A
. . . D
27A
D
26A
D
25A
. . . D
18A
D
17A
D
16A
. . . D
9A
D
8A
D
7A
. . . D
0A
H
L
H
X
AF
2
Offset
1
X
AE
2
Offset
1
X
AF
1
Offset
1
X
AE
1
Offset
1
CONTROL REGISTER: (WRITE-ONLY) PARITY EVEN/ODD
D
35A
D
1A
D0A
H
L
L
X...
...X
Parity Mode
2
8-BIT AE
1
FLAG OFFSET REGISTER
D
35A
D
8A
D
7A
. . . D
0A
L
H
H
X...
...X
AE
1
Offset
1
8-BIT AF
1
FLAG OFFSET REGISTER
D
35A
D
8A
D
7A
. . . D
0A
L
H
L
X...
...X
AF
1
Offset
1
8-BIT AE
2
FLAG OFFSET REGISTER
D
35A
D
8A
D
7A
. . . D
0A
L
L
H
X...
...X
AE
2
Offset
1
8-BIT AF
2
FLAG OFFSET REGISTER
D
35A
D
8A
D
7A
. . . D
0A
L
L
L
X...
...X
AF
2
Offset
1
NOTES:
1.
All four programmable-flag-offset values are initialized to eight (8) during a reset operation.
2.
Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.
256
×
36
×
2 Bidirectional FIFO
LH543601
13
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