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參數資料
| 型號： | LH543601P-20 |
| 廠商： | Sharp Corporation |
| 英文描述： | 256 x 36 x 2 Bidirectional FIFO |
| 中文描述： | 256 × 36 × 2雙向先進先出 |
| 文件頁數： | 17/43頁 |
| 文件大小： | 360K |
| 代理商： | LH543601P-20 |
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TIMING DIAGRAMS
RS
A
CK
EN
HF, AF, FF, MBF
A
EF, AE
EH
t
ES
t
EH
t
ES
t
RS
t
EH
t
ES
t
EH
t
ES
t
CK
B
EN
B
RSS
t
RSH
t
RSS
t
RSS
t
RSH
t
RSS
t
RF
t
RF
t
NOTES:
1. RS overrides all other input signals, except for R/W
A
, EN
A
, and REQ
A
. It operates
asynchronously. RS operates whether or not EN
A
and/or EN
B
are asserted. However,
at least one rising edge and one falling edge of both CK
A
and CK
B
must occur while
RS is being asserted (is LOW), with timing as defined by t
RSS
and t
RSH
.
2. Otherwise, t
RSS
, t
RSH
need not be met unless the rising edge of CK
A
and/or CK
B
occurs while that clock is enabled.
3. The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte
parity at reset (HIGH).
4. The AE and AF flag offsets are initialized to eight locations from the boundary at reset.
543601-26
REQ
A
t
RQS
t
RQH
REQ
B
t
RQS
t
RQH
t
RQS
t
RQH
t
RQS
t
RQH
Figure 8. Reset Timing
256
×
36
×
2 Bidirectional FIFO
LH543601
17
相關PDF資料 |
PDF描述 |
|---|---|
| LH543601P-25 | 256 x 36 x 2 Bidirectional FIFO |
| LH543601P-30 | 256 x 36 x 2 Bidirectional FIFO |
| LH543601P-35 | 256 x 36 x 2 Bidirectional FIFO |
| LH543611 | 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO |
| LH543620 | 1024 x 36 Synchronous FIFO |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LH543601P-25 | 制造商:Sharp Microelectronics Corporation 功能描述: 制造商:Sharp Microelectronics Corporation 功能描述:512 X 36 BI-DIRECTIONAL FIFO, PQFP132 |
| LH543601P-30 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:256 x 36 x 2 Bidirectional FIFO |
| LH543601P-35 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:256 x 36 x 2 Bidirectional FIFO |
| LH543611 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO |
| LH543611M-18 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
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