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參數(shù)資料
| 型號(hào)： | LH543601M-20 |
| 廠商： | Sharp Corporation |
| 英文描述： | 256 x 36 x 2 Bidirectional FIFO |
| 中文描述： | 256 × 36 × 2雙向先進(jìn)先出 |
| 文件頁數(shù)： | 12/43頁 |
| 文件大?。?/td> | 360K |
| 代理商： | LH543601M-20 |
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chronized predictor of the Almost-Full Flag AF for write
operations, or as a synchronized predictor of the Almost-
Empty Flag AE for read operations.
Outside the ‘a(chǎn)lmost-full’ region and the ‘a(chǎn)lmost-empty’
region, ACK
A/B
remains continuously HIGH whenever
REQ
A/B
is held continuously HIGH. Within the ‘a(chǎn)lmost-full’
region or the ‘a(chǎn)lmost-empty’ region, ACK
A/B
occurs only
on every thirdcycle, to prevent an overrun of the FIFO’s
actual full or empty boundaries and to ensure that the t
FWL
(first write latency) and t
FRL
(first read latency) specifica-
tions are satisfied before ACK
A/B
is received.
The ‘a(chǎn)lmost-full region’ is defined as ‘that region, where
the Almost-Full Flag is being asserted’; and the ‘a(chǎn)lmost-
empty region’ as ‘that region, where the Almost-Empty
Flag is being asserted.’ Thus, the extent of these ‘a(chǎn)lmost’
regions depends on how the system has programmed the
offset values for the Almost-Full Flags and the Almost-
Empty Flags. If the system has not programmed them,
then these offset values remain at their default values,
eight in each case.
If a write attempt is unsuccessful because the corre-
sponding FIFO is full, or if a read attempt is unsuccessful
because the corresponding FIFO is empty, ACK
A/B
is not
asserted in response to REQ
A/B
.
If the REQ/ACK handshake is not used, then the
REQ
A/B
input may be used as a second enable input, at
a possible minor loss in maximum operating speed. In this
case, the ACK
A/B
output may be ignored.
WARNING:
Whether or not the REQ/ACK handshake is
being used, the REQ
A/B
input for a port mustbe asserted
for that port to function at all – for FIFO, mailbox, or
data-bypass operation.
Data Retransmit
A retransmit operation resets the read-address pointer of
the corresponding FIFO (#1 or #2) back to the first FIFO
physical memory location, so that data may be reread. The
write pointer is not affected. The status flags are updated;
and a block of up to 256 data words, which previously had
been written into and read from a FIFO, can be retrieved.
The block to be retransmitted is bounded by the first FIFO
memory location, and the FIFO memory location addressed
by the write pointer. FIFO #1 retransmit is initiated by
strobing the RT
1
pin LOW. FIFO #2 retransmit is initiated by
strobing the RT
2
pin LOW. Read and write operations to a
FIFO should be stopped while the corresponding Retrans-
mit signal is being asserted.
Parity Checking
The Parity Check Flags, PF
A
and PF
B
, are asserted
(LOW) whenever there is a parity error in the data word
present on the Port A data bus or the Port B data bus
respectively. The inputs to the parity-evaluation logic
come directly (via isolation transistors) from the data-bus
bonding pads in each case. Thus, PF
A
and PF
B
provide
parity-error indications for whatever 36-bit words are
present at Port A and Port B respectively, regardless of
whether those words originated within the LH543601 or
in the external system.
The four bytes of a 36-bit data word are grouped as D
0
–
D
8
, D
9
–
D
17
, D
18
– D
26
, and D
27
– D
35
. The parity of each
nine-bit byte is individually checked, and the four single-bit
parity indications are logically inclusive-ORed and inverted,
to produce the Parity-Flag output. Parity checking is initial-
ized for odd parity at reset, but can be reprogrammed for
even parity or for odd parity during operation. Control-Reg-
ister bit 00 (zero) selects the parity mode, odd or even.
(See Table 3.)
All nine bits of each byte are treated alike by the parity
logic. The byte parity over the nine bits is compared with
the Parity Mode bit in the Control Register, to generate a
byte-parity-error indication. Then, the four byte-parity-
error signals are NORed together, to compute the asser-
tive-LOW parity-flag value.
Word-Width Selection on Port B
The word width of data access on Port B is selected
by the WS
0
and WS
1
control inputs. WS
0
and WS
1
both
are tied HIGH for 36-bit access; they both are tied LOW
for single-byte access. For double-byte access, WS
0
is
tied HIGH and WS
1
is tied LOW. (See Table 2.)
In the single-byte-access or double-byte-access modes,
FIFO write operations on Port B essentially pack the data to
form 36-bit words, as viewed from Port A. Similarly, single-
byte or double-byte FIFO read operations on Port B essen-
tially unpack 36-bit words through a series of shift
operations. FIFO status flags are updated following the last
access which forms a complete 36-bit transfer.
Since the values for each status flag are computed by
logic directly associated with one of the two FIFO-memory
arrays, and not by logic associated with Port B, the flag
values reflect the array fullness situation in terms of com-
plete 36-bit words and not in terms of bytes or double bytes.
However, there is no such restriction for switching from
writing to reading, or from reading to writing, at Port B. As
long as t
RWS
, t
DS
, and t
A
are satisfied, R/W
B
may change
state after anysingle-byte or double-byte access, and not
only after a full 36-bit-word access.
Also, the word-width-matching feature continues to
operate properly in ‘loopback’ mode.
Note that the programmable word-width-matching fea-
ture is onlysupported for FIFO accesses. Mailbox and
Data Bypass operations do notsupport word-width
matching between Port A and Port B. Tables 2, 3, and 4,
and Figures 6a, 6b, 7a, and 7b summarize word-width
selection for Port B.
Table 2. Port B Word-Width Selection
WS
1
H
H
L
L
WS
0
H
L
H
L
PORT B DATA WIDTH
36-Bit
(Reserved)
18-Bit
9-Bit
OPERATIONAL DESCRIPTION (cont’d)
LH543601
256
×
36
×
2 Bidirectional FIFO
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH543601M-25 | 256 x 36 x 2 Bidirectional FIFO |
| LH543601M-30 | 256 x 36 x 2 Bidirectional FIFO |
| LH543601M-35 | 256 x 36 x 2 Bidirectional FIFO |
| LH543601P-20 | 256 x 36 x 2 Bidirectional FIFO |
| LH543601P-25 | 256 x 36 x 2 Bidirectional FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH543601M-25 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:256 x 36 x 2 Bidirectional FIFO |
| LH543601M-30 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:256 x 36 x 2 Bidirectional FIFO |
| LH543601M-35 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:256 x 36 x 2 Bidirectional FIFO |
| LH543601P-20 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:256 x 36 x 2 Bidirectional FIFO |
| LH543601P-25 | 制造商:Sharp Microelectronics Corporation 功能描述: 制造商:Sharp Microelectronics Corporation 功能描述:512 X 36 BI-DIRECTIONAL FIFO, PQFP132 |
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