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參數(shù)資料
| 型號(hào)： | LH532000B |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 2M (256K x 8/128K x 16) MROM |
| 中文描述： | 200萬(wàn)的CMOS（256 × 8/128K × 16）MROM |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大小： | 68K |
| 代理商： | LH532000B |
AC CHARACTERISTICS (V
CC
= 5 V
±
10%, T
A
= 0 to +70
°
C)
PARAMETER
SYMBOL
120 ns
150 ns
UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
Read cycle time
Address access time
Chip enable access time
Output enable delay time
Output hold time
CE to output in High-Z
OE to output in High-Z
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
t
OHZ
120
150
ns
ns
ns
ns
ns
ns
ns
120
120
55
150
150
70
5
10
55
55
70
70
1
NOTE:
1.
This is the time required for the output to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input rise/fall time
Input reference level
Output reference level
Output load condition
0.6 V to 2.4 V
10 ns
1.5 V
0.8 V and 2.2 V
1TTL +100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
t
OE
t
AA
(D
0
- D
15
)
t
OHZ
t
CHZ
532000B-3
t
RC
t
ACE
CE
t
OH
DATA VALID
(NOTE 1)
D
0
- D
7
OE/OE
1
OE/OE
1
(A
0
- A
16
)
A-
1
- A
16
1. Data becomes valid after t
, t
, and t
from address
input, chip enable or output enable, respectively have been met.
2. Applied to byte mode. Signals in parentheses apply to word mode.
NOTES:
(NOTE 1)
(NOTE 2)
(NOTE 2)
Figure 4. Timing Diagram
CMOS 2M MROM
LH532000B
5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH532000B-1 | 制造商:SHARP 制造商全稱(chēng):Sharp Electrionic Components 功能描述:CMOS 2M (256K x 8/128K x 16) MROM |
| LH532000BD-1 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x8 or x16 ROM (Mask Programmable) |
| LH532000BD-12 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x8 or x16 ROM (Mask Programmable) |
| LH532000BD-15 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x8 or x16 ROM (Mask Programmable) |
| LH532000BD-S150 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x8 or x16 ROM (Mask Programmable) |
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