
531024-3
40
V
CC
MEMORY
MATRIX
(65,536 x 16)
SENSE AMPLIFIER
30
GND
20
OE
A
CE
A
CE
BUFFER
2
TIMING
GENERATOR
A
5
A
4
A
3
A
2
A
1
A
0
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
15
33
32
29
28
26
25
24
23
22
21
31
27
36
35
34
37
11
OE
BUFFER
COLUMN SELECTOR
D
5
D
4
D
3
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
6
D
7
D
15
D
2
D
1
D
0
OUTPUT BUFFER
5 4
3
6
7
8
9
10
12
13
14
15
16
17
18
19
NOTE:
Pin numbers apply to the 40-pin DIP or SOP.
Figure 3. LH531024 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
A
0
– A
15
D
0
– D
15
CE
Address input
Data output
Chip Enable input
SIGNAL
PIN NAME
OE
V
CC
GND
Output enable input
Power supply (+5 V)
Ground
LH531024
CMOS 1M MROM
2