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參數(shù)資料
| 型號(hào)： | LH521028A |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 64K x 18 Static RAM |
| 中文描述： | 64K的× 18的CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | LH521028A |
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TIMING DIAGRAMS – READ CYCLE
Read Cycle No. 1
(Unlatched Address Controlled Read)
Chip is in Read Mode: ALE is HIGH (transparent
mode), E and G are LOW. Read cycle timing is referenced
from when all addresses are stable until the first address
transition. Following a W-controlled Write cycle, t
WA
and
t
AA
must both be satisfied to ensure valid data. Cross-
hatched portion of Data Out implies that data lines are in
the Low-Z state but the data is not guaranteed to be valid
until t
AA
.
Read Cycle No. 2
(Unlatched Chip Enable Controlled Read)
Chip is in Read Mode: ALE is HIGH (transparent
mode). Read cycle timing is referenced from when E, S
,
and
G are stable until the first address transition. Cross-
hatched portion of Data Out implies that data lines are in
the Low-Z state but the data is not guaranteed to be valid.
t
RC
VALID ADDRESS
t
AA
t
OH
VALID DATA
ADDRESS
DQ
521028-2
PREVIOUS DATA
t
WA
W
Figure 4. Read Cycle No. 1
t
SLZ
t
GLZ
t
ELZ
t
SA
VALID DATA
t
GHZ
S
L
, S
H
G
DQ
VALID ADDRESS
ADDRESS
W
t
RCS
t
RCH
t
EA
t
EHZ
t
GA
t
SHZ
E
521028-3
Figure 5. Read Cycle No. 2
LH521028A
CMOS 64K
×
18 Static RAM
8
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|---|---|
| LH521028 | CMOS 64K x 18 Static RAM |
| LH52253K35 | CMOS 64K X 4 STATIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH521028AU-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
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