參數(shù)資料
型號: LH5116N-10
廠商: Sharp Corporation
英文描述: CMOS 16K (2K x 8) Static RAM
中文描述: 的CMOS 16K的(2K × 8)靜態(tài)RAM
文件頁數(shù): 6/10頁
文件大?。?/td> 87K
代理商: LH5116N-10
A
0
- A
10
D
OUT
t
WC
t
AW
t
CW
t
WP
t
WHZ
t
OW
t
DH
t
DW
t
WR
(NOTE 3)
t
AS
(NOTE 2)
(NOTE 4)
5116-4
WE
CE
D
IN
(NOTE 5)
(NOTE 6)
1. WE must be HIGH when there is a change in A
- A
.
2. When CE and WE are both LOW at the same time, write occurs during the period t
.
3. t
is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.
4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.
5. D
outputs data with the same logic level as the input data of this write cycle.
6. If CE is LOW during this period, the input/output pin is in the output state. During this state, input
signals of opposite logic level must not be applied.
OE = 'LOW'
NOTES:
Figure 5. Write Cycle 1
A
0
- A
10
D
OUT
t
WC
t
AW
(NOTE 2)
WE
D
IN
t
CW
t
WP
t
OHZ
t
OW
WR
t
DH
t
DW
(Nt
t
AS
t
OLZ
OE
CE
(NOTE 5)
(NOTE 6)
(NOTE 4)
5116-5
1. WE must be HIGH when there is a change in A
- A
.
2. When CE and WE are both LOW at the same time, write occurs during the period t
.
3. t
is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.
4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.
5. D
outputs data with the same logic level as the input data of this write cycle.
6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input
signals of opposite logic level must not be applied.
NOTES:
Figure 6. Write Cycle 2
LH5116/H
CMOS 16K (2K
×
8) Static RAM
6
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