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參數資料
| 型號： | LH28F800SGHR-L70 |
| 英文描述： | x16 Flash EEPROM |
| 中文描述： | x16閃存EEPROM |
| 文件頁數： | 23/56頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LH28F800SGHR-L70 |
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LH28F160S5-L/S5H-L
- 23 -
Table 13.1 Status Register Definition
ECBLBS
WSBLBS
5
4
WSMS
7
BESS
6
VPPS
3
WSS
2
DPS
1
R
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 =
ERASE AND CLEAR BLOCK LOCK-BITS STATUS
(ECBLBS)
1 = Error in Erase or Clear Block Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
SR.4 =
WRITE AND SET BLOCK LOCK-BIT STATUS
(WSBLBS)
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
SR.2 = WRITE SUSPEND STATUS (WSS)
1 = Write Suspended
0 = Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Lock-Bit and/or WP# Lock Detected,
Operation Abort
0 = Unlock
SR.0 =
RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES :
Check STS or SR.7 to determine block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
completion.
SR.6-0 are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, (multi) word/byte write, block lock-bit configuration or
STS configuration attempt, an improper command sequence
was entered.
SR.3 does not provide a continuous indication of V
PP
level.
The WSM interrogates and indicates the V
PP
level only after
block erase, full chip erase, (multi) word/byte write or block
lock-bit configuration command sequences. SR.3 is not
guaranteed to reports accurate feedback only when V
PP
≠
V
PPH1
.
SR.1 does not provide a continuous indication of block lock-bit
values. The WSM interrogates block lock-bit, and WP# only
after block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration command sequences. It informs
the system, depending on the attempted operation, if the block
lock-bit is set and/or WP# is not V
IH
. Reading the block lock
configuration codes after writing the Read Identifier Codes
command indicates block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
Table 13.2 Extended Status Register Definition
R
R
5
4
SMS
7
R
6
R
3
R
2
R
1
R
0
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available
XSR.6-0 =
RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES :
After issue a Multi Word/Byte Write command : XSR.7
indicates that a next Multi Word/Byte Write command is
available.
XSR.6-0 are reserved for future use and should be masked
out when polling the extended status register.
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相關代理商/技術參數 |
參數描述 |
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| LH28F800SG-L | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memory |
| LH28F800SG-L10 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800SG-L70 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800SGN-L10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM |
| LH28F800SGN-L100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM |
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