參數(shù)資料
型號: LH28F800BJB-PBTL90
英文描述: Flash ROM
中文描述: 閃存ROM
文件頁數(shù): 24/56頁
文件大小: 373K
代理商: LH28F800BJB-PBTL90
LH28F160S5-L/S5H-L
- 24 -
Block Erase
Complete
Start
Write 70H
Read
Status Register
0
0
Yes
No
SR.7 =
1
SR.7 =
1
Write 20H,
Block Address
Write D0H,
Block Address
Suspend Block
Erase Loop
Read
Status Register
Full Status
Check if Desired
SR.3 =
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
V
PP
Range Error
1
0
SR.1 =
Device Protect Error
1
0
BUS
OPERATION
COMMAND
COMMENTS
Standby
Standby
Check SR.1
1 = Device Protect Detect
WP# = V
IL
, Block Lock-Bit is Set
Only required for systems implement-
ing block lock-bit configuration
Check SR.5
1 = Block Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Block Erase
Successful
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after
a sequence of block erasures.
Write FFH after the last block erase operation to place device
in read array mode.
SR.4, 5 =
Command Sequence
Error
1
0
SR.5 =
Block Erase Error
1
0
Standby
Check SR.3
1 = V
PP
Error Detect
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
BUS
OPERATION
Write
Read
Standby
Standby
COMMAND
Read Status
Register
COMMENTS
Data = 70H
Addr = X
Status Register Data
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.7
1 = WSM Ready
0 = WSM Busy
Erase
Confirm
Erase Setup
Write
Write
Read
Data = D0H
Addr = Within Block to be Erased
Data = 20H
Addr = Within Block to be Erased
Suspend
Block Erase
Fig. 3 Automated Block Erase Flowchart
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
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