參數(shù)資料
型號(hào): LH28F800BJB-PBTL10
英文描述: Flash ROM
中文描述: 閃存ROM
文件頁(yè)數(shù): 50/56頁(yè)
文件大?。?/td> 373K
代理商: LH28F800BJB-PBTL10
LH28F160S5-L/S5H-L
- 50 -
V
CC
= 5.0±0.25 V, 5.0±0.5 V, T
A
= 0 to +70°C or
–40 to +85°C
6.2.8 BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND
BLOCK LOCK-BIT CONFIGURATION PERFORMANCE
(NOTE 3, 4)
NOTES :
1.
Typical values measured at T
A
= +25°C and nominal
voltages. Assumes corresponding block lock-bits are not
set. Subject to change based on device characterization.
2.
Excludes system-level overhead.
3.
These performance numbers are valid for all speed
versions.
Sampled, not 100% tested.
4.
SYMBOL
PARAMETER
NOTE
V
CC
= 5.0±0.5 V
TYP.
(NOTE 1)
UNIT
MIN.
MAX.
t
WHQV1
t
EHQV1
t
WHQV1
t
EHQV1
Word/Byte Write Time (using W/B write, in word mode)
2
9.24
TBD
μs
Word/Byte Write Time (using W/B write, in byte mode)
2
9.24
TBD
μs
Word/Byte Write Time (using multi word/byte write)
Block Write Time (using W/B write, in word mode)
Block Write Time (using W/B write, in byte mode)
Block Write Time (using multi word/byte write)
2
2
2
2
2
TBD
3.7
7.5
1.5
μs
s
s
s
0.31
0.61
0.13
t
WHQV2
t
EHQV2
Block Erase Time
2
0.34
10
s
Full Chip Erase Time
10.9
TBD
s
t
WHQV3
t
EHQV3
t
WHQV4
t
EHQV4
t
WHRH1
t
EHRH1
t
WHRH2
t
EHRH2
Set Block Lock-Bit Time
2
9.24
TBD
μs
Clear Block Lock-Bits Time
2
0.34
TBD
s
Write Suspend Latency Time to Read
5.6
7
μs
Erase Suspend Latency Time to Read
9.4
13.1
μs
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