參數(shù)資料
型號: LH28F800BGXX-XL12
廠商: Sharp Corporation
英文描述: 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
中文描述: 8 M位(512 KB的× 16)SmartVoltage閃存
文件頁數(shù): 33/38頁
文件大小: 328K
代理商: LH28F800BGXX-XL12
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
33
NOTES:
CE
is defined as the latter of CE
0
or CE
1
going Low or the first of CE
0
or CE
1
going High.
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE
for all Command Write Operations.
AC Characteristics for CE
- Controlled Command Write Operations
1
(Continued)
T
A
= 0°C to +70°C
SYMBOL
PARAMETER
V
CC
= 5.0 V ± 0.25 V
V
CC
= 5.0 V ± 0.5 V
UNITS
NOTE
TYP.
MIN.
MAX.
TYP.
MIN.
MAX.
t
AVAV
Write Cycle Time
70
80
ns
t
PHWL
RP
Setup to WE Going Low
480
480
ns
3
t
VPEH
V
PP
Setup to CE
Going High
100
100
ns
3
t
WLEL
WE Setup to CE
Going Low
0
0
ns
t
AVEH
Address Setup to CE
Going High
50
50
ns
2, 6
t
DVEH
Data Setup to CE
Going High
50
50
ns
2, 6
t
ELEH
CE
Pulse Width
40
50
ns
t
EHDX
Data Hold from CE
High
0
0
ns
2
t
EHAX
Address Hold from CE
High
10
10
ns
2
t
EHWH
WE Hold from CE
High
10
10
ns
t
EHEL
CE
Pulse Width High
30
30
ns
t
GHEL
Read Recovery before Write
0
ns
t
EHRL
CE
High to RY
/BY
Going Low
100
100
ns
t
RHPL
RP
Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY
/BY
High
0
0
ns
3
t
PHEL
RP
High Recovery to CE
Going Low
1
1
μs
t
EHGL
Write Recovery before Read
60
65
ns
t
QVVL
V
PP
Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY
/BY
High
0
0
μs
t
EHQV1
t
EHQV2
Duration of Word/Byte Write Operation
8
4.5
4.5
μs
4, 5
Duration of Block Erase Operation
0.3
0.3
s
4
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