參數(shù)資料
型號: LH28F800BGHR-BL85
廠商: Sharp Corporation
英文描述: 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
中文描述: 8 M位(512 KB的× 16)SmartVoltage閃存
文件頁數(shù): 31/38頁
文件大?。?/td> 328K
代理商: LH28F800BGHR-BL85
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
31
Figure 15. AC Waveforms for Command Write Operations
ADDRESSES (A)
(NOTE 1)
V
IH
V
IL
A
IN
A = RA
V
IH
V
IL
A
IN
A = RA
D
IN
D
IN
D
IN
D
IN
D
OUT
CE
X
(E)
(NOTE 4)
V
IH
V
IL
OE (G)V
IH
V
IL
WE (W)V
IH
V
IL
DATA (D/Q)V
IH
V
IL
RY/BY (R)V
OH
V
OL
RP (P)V
IH
V
IL
V
PP
(V)V
PPH
V
PPL
t
AVAV
t
AVAV
t
WHGL
t
WHWL
t
WLWH
t
DVWH
t
PHWL
t
RHPL
t
QVVL
ADDRESSES (A)
(NOTE 2)
t
AVWH
t
WHAX
t
AVWH
t
WHAX
t
ELWL
t
WHEH
t
WHQV1, 2
t
GHWL
t
WHDX
t
WHRL
(NOTE 5)
t
VPWH
28F800SUR-13
(NOTE 3)
HIGH-Z
WRITE
DATA-WRITE
OR ERASE
SETUP COMMAND
DEEP
POWER-DOWN
WRITE VALID
ADDRESS AND DATA
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
WRITE READ
EXTENDED
REGISTER
COMMAND
READ
EXTENDED
STATUS
REGISTER DATA
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CE
X
is defined as the latter of CE
0
or CE
1
going LOW or the first of CE
0
or CE
1
going HIGH.
5. RP low transition is only to show t
RHPL
; not valid for above Read and Write cycles.
READ
COMPATIBLE
STATUS
REGISTER DATA
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